From: Timo Kokkonen <redacted>
Date: Sat, 3 Oct 2020 23:35:10 +0000 (-0700)
Subject: rigol-dg: Fix reading current output signal duty cycle value.
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=d999f2b61e96882aed01fd58cbf45e773b855009;p=libsigrok.git

rigol-dg: Fix reading current output signal duty cycle value.

Reading output signal duty cycle value didn't always work, since it relied
on old (cached) information about the currently active waveform. Changed to
always query channel status so this won't happen anymore.
---

diff --git a/src/hardware/rigol-dg/api.c b/src/hardware/rigol-dg/api.c
index efe7db62..43121aed 100644
--- a/src/hardware/rigol-dg/api.c
+++ b/src/hardware/rigol-dg/api.c
@@ -490,6 +490,8 @@ static int config_get(uint32_t key, GVariant **data,
 				*data = g_variant_new_double(ch_status->phase);
 			break;
 		case SR_CONF_DUTY_CYCLE:
+			if ((ret = rigol_dg_get_channel_state(sdi, cg)) != SR_OK)
+				break;
 			if (ch_status->wf == WF_SQUARE) {
 				cmd = PSG_CMD_GET_DCYCL_SQUARE;
 			} else if (ch_status->wf == WF_PULSE) {