From: Uwe Hermann Date: Tue, 14 Feb 2012 20:22:55 +0000 (+0100) Subject: Initial version (work in progress). X-Git-Tag: sigrok-firmware-fx2lafw-0.1.0~84 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=d5f5ea7394647699061f7185c884328defff9b7d;p=sigrok-firmware-fx2lafw.git Initial version (work in progress). This does not work, yet. --- d5f5ea7394647699061f7185c884328defff9b7d diff --git a/COPYING b/COPYING new file mode 100644 index 00000000..d511905c --- /dev/null +++ b/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..7a9f2945 --- /dev/null +++ b/Makefile @@ -0,0 +1,26 @@ +## +## This file is part of the fx2lafw project. +## +## Copyright (C) 2011-2012 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +SOURCES = fx2lafw.c +A51_SOURCES = dscr.a51 +BASENAME = fx2lafw + +include fx2lib/lib/fx2.mk + diff --git a/README b/README new file mode 100644 index 00000000..2295a7ec --- /dev/null +++ b/README @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------ +fx2lafw +------------------------------------------------------------------------------ + +fx2lafw is a free/libre/open-source firmware for logic analyzers based on +the Cypress EZ-USB FX2(LP) chip. + +It is licensed under the terms of the GNU GPL (version 2 or later). + +Requirements +------------ + +In order to build fx2lafw you need the 'sdcc' compiler. + +On Debian you can install it via: + + $ apt-get install sdcc + +In order to transfer the firmware onto the FX2 chip, you can use cycfx2prog: + + $ apt-get install cycfx2prog + +Building +-------- + + $ git clone ... + $ cd fx2lafw + $ git clone git://github.com/mulicheng/fx2lib.git + $ make + +Usage +----- + + $ cycfx2prog -id=vvvv:pppp prg:build/fx2lafw.ihx reset run delay:100 + +You have to provide the USB VID/PID of the FX2 device (before firmware +upload) using the -id parameter. + +Website +------- + +See the fx2lafw website for further information: + + http://sigrok.org/wiki/Fx2lafw + diff --git a/dscr.a51 b/dscr.a51 new file mode 100644 index 00000000..3a5e9dcc --- /dev/null +++ b/dscr.a51 @@ -0,0 +1,227 @@ +;; +;; This file is part of the fx2lafw project. +;; +;; Copyright (C) 2011-2012 Uwe Hermann +;; +;; This program is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2 of the License, or +;; (at your option) any later version. +;; +;; This program is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with this program; if not, write to the Free Software +;; Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +;; + +.module DEV_DSCR + +; Descriptor types +DSCR_DEVICE_TYPE = 1 +DSCR_CONFIG_TYPE = 2 +DSCR_STRING_TYPE = 3 +DSCR_INTERFACE_TYPE = 4 +DSCR_ENDPOINT_TYPE = 5 +DSCR_DEVQUAL_TYPE = 6 + +; Descriptor lengths +DSCR_INTERFACE_LEN = 9 +DSCR_ENDPOINT_LEN = 7 + +; Endpoint types +ENDPOINT_TYPE_CONTROL = 0 +ENDPOINT_TYPE_ISO = 1 +ENDPOINT_TYPE_BULK = 2 +ENDPOINT_TYPE_INT = 3 + +.globl _dev_dscr, _dev_qual_dscr, _highspd_dscr, _fullspd_dscr, _dev_strings, _dev_strings_end +.area DSCR_AREA (CODE) + +; ----------------------------------------------------------------------------- +; Device descriptor +; ----------------------------------------------------------------------------- +_dev_dscr: + .db dev_dscr_end - _dev_dscr + .db DSCR_DEVICE_TYPE + .dw 0x0002 ; USB 2.0 + .db 0xff ; Class (vendor specific) + .db 0xff ; Subclass (vendor specific) + .db 0xff ; Protocol (vendor specific) + .db 64 ; Max. EP0 packet size + .dw 0x6666 ; Manufacturer ID (0x6666) + .dw 0x1900 ; Product ID (0x0019) + .dw 0x0100 ; Product version (0.01) + .db 1 ; Manufacturer string index + .db 2 ; Product string index + .db 0 ; Serial number string index (none) + .db 1 ; Number of configurations +dev_dscr_end: + +; ----------------------------------------------------------------------------- +; Device qualifier (for "other device speed") +; ----------------------------------------------------------------------------- +_dev_qual_dscr: + .db dev_qualdscr_end - _dev_qual_dscr + .db DSCR_DEVQUAL_TYPE + .dw 0x0002 ; USB 2.0 + .db 0xff ; Class (vendor specific) + .db 0xff ; Subclass (vendor specific) + .db 0xff ; Protocol (vendor specific) + .db 64 ; Max. EP0 packet size + .db 1 ; Number of configurations + .db 0 ; Extra reserved byte +dev_qualdscr_end: + +; ----------------------------------------------------------------------------- +; High-Speed configuration descriptor +; ----------------------------------------------------------------------------- +_highspd_dscr: + .db highspd_dscr_end - _highspd_dscr + .db DSCR_CONFIG_TYPE + ; Total length of the configuration (1st line LSB, 2nd line MSB) + .db (highspd_dscr_realend - _highspd_dscr) % 256 + .db (highspd_dscr_realend - _highspd_dscr) / 256 + .db 1 ; Number of interfaces + .db 1 ; Configuration number + .db 0 ; Configuration string (none) + .db 0x80 ; Attributes (bus powered, no wakeup) + .db 0x32 ; Max. power (100mA) +highspd_dscr_end: + + ; Interfaces (only one in our case) + .db DSCR_INTERFACE_LEN + .db DSCR_INTERFACE_TYPE + .db 0 ; Interface index + .db 0 ; Alternate setting index + .db 2 ; Number of endpoints + .db 0xff ; Class (vendor specific) + .db 0xff ; Subclass (vendor specific) + .db 0xff ; Protocol (vendor specific) + .db 0 ; String index (none) + + ; Endpoint 1 (OUT) + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x01 ; EP number (1), direction (OUT) + .db ENDPOINT_TYPE_BULK ; Endpoint type (bulk) + .db 0x00 ; Max. packet size, LSB (512 bytes) + .db 0x02 ; Max. packet size, MSB (512 bytes) + .db 0x00 ; Polling interval + + ; Endpoint 2 (IN) + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x82 ; EP number (2), direction (IN) + .db ENDPOINT_TYPE_BULK ; Endpoint type (bulk) + .db 0x00 ; Max. packet size, LSB (512 bytes) + .db 0x02 ; Max. packet size, MSB (512 bytes) + .db 0x00 ; Polling interval + +highspd_dscr_realend: + + .even + +; ----------------------------------------------------------------------------- +; Full-Speed configuration descriptor +; ----------------------------------------------------------------------------- +_fullspd_dscr: + .db fullspd_dscr_end - _fullspd_dscr + .db DSCR_CONFIG_TYPE + ; Total length of the configuration (1st line LSB, 2nd line MSB) + .db (fullspd_dscr_realend - _fullspd_dscr) % 256 + .db (fullspd_dscr_realend - _fullspd_dscr) / 256 + .db 1 ; Number of interfaces + .db 1 ; Configuration number + .db 0 ; Configuration string (none) + .db 0x80 ; Attributes (bus powered, no wakeup) + .db 0x32 ; Max. power (100mA) +fullspd_dscr_end: + + ; Interfaces (only one in our case) + .db DSCR_INTERFACE_LEN + .db DSCR_INTERFACE_TYPE + .db 0 ; Interface index + .db 0 ; Alternate setting index + .db 2 ; Number of endpoints + .db 0xff ; Class (vendor specific) + .db 0xff ; Subclass (vendor specific) + .db 0xff ; Protocol (vendor specific) + .db 0 ; String index (none) + + ; Endpoint 1 (OUT) + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x01 ; EP number (1), direction (OUT) + .db ENDPOINT_TYPE_BULK ; Endpoint type (bulk) + .db 0x40 ; Max. packet size, LSB (64 bytes) + .db 0x00 ; Max. packet size, MSB (64 bytes) + .db 0x00 ; Polling interval + + ; Endpoint 2 (IN) + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x82 ; EP number (2), direction (IN) + .db ENDPOINT_TYPE_BULK ; Endpoint type (bulk) + .db 0x40 ; Max. packet size, LSB (64 bytes) + .db 0x00 ; Max. packet size, MSB (64 bytes) + .db 0x00 ; Polling interval + +fullspd_dscr_realend: + + .even + +; ----------------------------------------------------------------------------- +; Strings +; ----------------------------------------------------------------------------- + +_dev_strings: + +_string0: + .db string0end - _string0 + .db DSCR_STRING_TYPE + .db 0x09, 0x04 ; Language code 0x0409 (English) +string0end: + +_string1: + .db string1end - _string1 + .db DSCR_STRING_TYPE + .ascii 's' + .db 0 + .ascii 'i' + .db 0 + .ascii 'g' + .db 0 + .ascii 'r' + .db 0 + .ascii 'o' + .db 0 + .ascii 'k' + .db 0 +string1end: + +_string2: + .db string2end - _string2 + .db DSCR_STRING_TYPE + .ascii 'f' + .db 0 + .ascii 'x' + .db 0 + .ascii '2' + .db 0 + .ascii 'l' + .db 0 + .ascii 'a' + .db 0 + .ascii 'f' + .db 0 + .ascii 'w' + .db 0 +string2end: + +_dev_strings_end: + .dw 0x0000 + diff --git a/fx2lafw.c b/fx2lafw.c new file mode 100644 index 00000000..0488cb7e --- /dev/null +++ b/fx2lafw.c @@ -0,0 +1,361 @@ +/* + * This file is part of the fx2lafw project. + * + * Copyright (C) 2011-2012 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. + * + * It is written in C, using fx2lib as helper library, and sdcc as compiler. + * The code is licensed under the terms of the GNU GPL, version 2 or later. + * + * Technical notes: + * + * - We use the FX2 in GPIF mode to sample the data (asynchronously). + * - We use the internal 48MHz clock for GPIF. + * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7. + * Support for 16 channels is not yet included, but might be added later. + * - Endpoint 2 is used for data transfers from FX2 to host. + * - The endpoint is quad-buffered. + * + * Documentation: + * + * - See http://sigrok.org/wiki/Fx2lafw + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SYNCDELAY() SYNCDELAY4 + +/* ... */ +volatile bit got_sud; + +/* GPIF terminology: DP = decision point, NDP = non-decision-point */ + +/* GPIF waveforms */ +static const BYTE wavedata[128] = { + /* Waveform 0: */ + + /* TODO: This is just a dummy entry, fill with useful data. */ + + /* S0-S6: LENGTH/BRANCH */ + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + /* TRM says "reserved", but GPIF designer always puts a 0x07 here. */ + 0x07, + /* S0-S6: OPCODE */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* Reserved */ + 0x00, + /* S0-S6: OUTPUT */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* Reserved */ + 0x00, + /* S0-S6: LOGIC FUNCTION (not used for NDPs) */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* TRM says "reserved", but GPIF designer always puts a 0x3f here. */ + 0x3f, + + /* TODO: Must unused waveforms be "valid"? */ + + /* Waveform 1 (unused): */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Waveform 2 (unused): */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Waveform 3 (unused): */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static void gpif_setup_registers(void) +{ + /* TODO. Value probably irrelevant, as we don't use RDY* signals? */ + GPIFREADYCFG = 0; + + /* + * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. + * TODO: Probably irrelevant, as we don't use CTL0-CTL5? + */ + GPIFCTLCFG = 0; + + /* When GPIF is idle, tri-state the data bus. */ + /* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */ + GPIFIDLECS = (1 << 0); + + /* When GPIF is idle, set CTL0-CTL5 to 0. */ + GPIFIDLECTL = 0; + + /* + * Map index 0 in wavedata[] to FIFORD. The rest is assigned too, + * but not used by us. + * + * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index, + * [3:2] = FIFOWR index, [1:0] = FIFORD index + */ + GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0); + + /* Contains RDY* pin values. Read-only according to TRM. */ + GPIFREADYSTAT = 0; +} + +static void gpif_write_waveforms(void) +{ + int i; + + /* + * Write the four waveforms into the respective WAVEDATA register + * locations (0xe400 - 0xe47f) using the FX2's autopointer feature. + */ + AUTOPTRSETUP = 0x07; /* Increment autopointers 1 & 2. */ + AUTOPTRH1 = MSB((WORD)wavedata); /* Source is the 'wavedata' array. */ + AUTOPTRL1 = LSB((WORD)wavedata); + AUTOPTRH2 = 0xe4; /* Dest is WAVEDATA (0xe400). */ + AUTOPTRL2 = 0x00; + for (i = 0; i < 128; i++) + EXTAUTODAT2 = EXTAUTODAT1; +} + +static void gpif_init_addr_pins(void) +{ + /* + * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of + * PORTC[7:0] and PORTE[7]), and output an initial address (zero). + * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E. + */ + PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */ + OEC = 0xff; /* Configure PORTC[7:0] as outputs. */ + PORTECFG |= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */ + OEE |= 0x80; /* Configure PORTE[7] as output. */ + SYNCDELAY(); + GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */ + SYNCDELAY(); + GPIFADRH = 0x00; /* Clear GPIFADR[8]. */ +} + +static void gpif_init_flowstates(void) +{ + /* Clear all flowstate registers, we don't use this functionality. */ + FLOWSTATE = 0; + FLOWLOGIC = 0; + FLOWEQ0CTL = 0; + FLOWEQ1CTL = 0; + FLOWHOLDOFF = 0; + FLOWSTB = 0; + FLOWSTBEDGE = 0; + FLOWSTBHPERIOD = 0; +} + +static void gpif_init_la(void) +{ + /* + * Setup the FX2 in GPIF master mode, using the internal clock + * (non-inverted) at 48MHz, and using async sampling. + */ + IFCONFIG = 0xee; + + /* Abort currently executing GPIF waveform (if any). */ + GPIFABORT = 0xff; + + /* Setup the GPIF registers. */ + gpif_setup_registers(); + + /* Write the four GPIF waveforms into the WAVEDATA register. */ + gpif_write_waveforms(); + + /* Initialize GPIF address pins, output initial values. */ + gpif_init_addr_pins(); + + /* Initialize flowstate registers (not used by us). */ + gpif_init_flowstates(); +} + +static void setup_endpoints(void) +{ + /* Setup EP1 (OUT). */ + EP1OUTCFG = (1 << 7) | /* EP is valid/activated */ + (0 << 6) | /* Reserved */ + (1 << 5) | (0 << 4) | /* EP Type: bulk */ + (0 << 3) | /* Reserved */ + (0 << 2) | /* Reserved */ + (0 << 1) | (0 << 0); /* Reserved */ + SYNCDELAY(); + + /* Setup EP2 (IN). */ + EP2CFG = (1 << 7) | /* EP is valid/activated */ + (1 << 6) | /* EP direction: IN */ + (1 << 5) | (0 << 4) | /* EP Type: bulk */ + (0 << 3) | /* EP buffer size: 512 */ + (0 << 2) | /* Reserved. */ + (0 << 1) | (0 << 0); /* EP buffering: quad buffering */ + SYNCDELAY(); + + /* Disable all other EPs (EP4, EP6, and EP8). */ + EP4CFG &= ~bmVALID; + SYNCDELAY(); + EP6CFG &= ~bmVALID; + SYNCDELAY(); + EP8CFG &= ~bmVALID; + SYNCDELAY(); + + /* Reset the FIFOs of EP1 and EP2. */ + /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ + RESETFIFO(0x01) + RESETFIFO(0x02) + + /* Set the GPIF flag for EP2 to 'empty'. */ + EP2GPIFFLGSEL = (0 << 1) | (1 << 1); + SYNCDELAY(); +} + +BOOL handle_vendorcommand(BYTE cmd) +{ + (void)cmd; + return FALSE; +} + +BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) +{ + /* We only support interface 0, alternate interface 0. */ + if (ifc != 0) + return FALSE; + + *alt_ifc = 0; + return TRUE; +} + +BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) +{ + /* We only support interface 0, alternate interface 0. */ + if (ifc != 0 || alt_ifc != 0) + return FALSE; + + /* Perform procedure from TRM, section 2.3.7: */ + + /* (1) TODO. */ + + /* (2) Reset data toggles of the EPs in the interface. */ + /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ + RESETTOGGLE(0x01); + RESETTOGGLE(0x82); + + /* (3) Restore EPs to their default conditions. */ + /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ + RESETFIFO(0x01); + /* TODO */ + RESETFIFO(0x02); + /* TODO */ + + /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ + + return TRUE; +} + +BYTE handle_get_configuration(void) +{ + /* We only support configuration 1. */ + return 1; +} + +BOOL handle_set_configuration(BYTE cfg) +{ + /* We only support configuration 1. */ + return (cfg == 1) ? TRUE : FALSE; +} + +void sudav_isr(void) interrupt SUDAV_ISR +{ + got_sud = TRUE; + CLEAR_SUDAV(); +} + +void sof_isr(void) interrupt SOF_ISR using 1 +{ + CLEAR_SOF(); +} + +void usbreset_isr(void) interrupt USBRESET_ISR +{ + handle_hispeed(FALSE); + CLEAR_USBRESET(); +} + +void hispeed_isr(void) interrupt HISPEED_ISR +{ + handle_hispeed(TRUE); + CLEAR_HISPEED(); +} + +void main(void) +{ + /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ + REVCTL = (1 << 1) | (1 << 0); + + got_sud = FALSE; + + /* Renumerate. */ + RENUMERATE_UNCOND(); + + SETCPUFREQ(CLK_48M); + + USE_USB_INTS(); + + /* TODO: Does the order of the following lines matter? */ + ENABLE_SUDAV(); + ENABLE_SOF(); + ENABLE_HISPEED(); + ENABLE_USBRESET(); + + /* Global (8051) interrupt enable. */ + EA = 1; + + /* Setup the endpoints. */ + setup_endpoints(); + + /* Put the FX2 into GPIF master mode and setup the GPIF. */ + gpif_init_la(); + + /* TODO */ + /* Initiate a GPIF read. */ + (void)EP2GPIFTRIG; +#if 0 + /* TODO: This seems to hang? */ + gpif_fifo_read(GPIF_EP2); +#endif + + while (1) { + if (got_sud) { + handle_setupdata(); + got_sud = FALSE; + } + } +}