From: Uwe Hermann <redacted>
Date: Sat, 14 Feb 2015 18:08:39 +0000 (+0100)
Subject: rigol-ds: Add missing 20/50/100V vdiv entries.
X-Git-Tag: libsigrok-0.4.0~641
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=d50725e0126a5d52d97e7ea49e37c66c15108156;p=libsigrok.git

rigol-ds: Add missing 20/50/100V vdiv entries.

These are available on e.g. Rigol DS1102E (or "upgraded" DS1052E).

Without this, if one of the channels happens to have been set to
one of the missing vdiv settings frontends (e.g. PulseView) will
have some trouble using the scope:

  sr: hwdriver: sr_config_get(): key 30012 (vdiv) sdi 0x11bcb70 cg CH1
  sr: rigol-ds: Negative vdiv index: -1.
  std::exception
---

diff --git a/src/hardware/rigol-ds/api.c b/src/hardware/rigol-ds/api.c
index d748e6d4..3ce237d7 100644
--- a/src/hardware/rigol-ds/api.c
+++ b/src/hardware/rigol-ds/api.c
@@ -113,6 +113,9 @@ static const uint64_t vdivs[][2] = {
 	{ 2, 1 },
 	{ 5, 1 },
 	{ 10, 1 },
+	{ 20, 1 },
+	{ 50, 1 },
+	{ 100, 1 },
 };
 
 #define NUM_TIMEBASE  ARRAY_SIZE(timebases)