From: Tim Hatch <redacted>
Date: Sun, 2 Nov 2014 23:29:38 +0000 (-0800)
Subject: saleae-logic16: Downgrade error during capture to a message.
X-Git-Tag: libsigrok-0.4.0~719
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=cd3c4df35acdde1920fcaac92c0fd85591167e7a;p=libsigrok.git

saleae-logic16: Downgrade error during capture to a message.

Some clone doesn't set this to the exact same value, and both bits in 0x48 are
marked as unknown at
http://sigrok.org/wiki/Saleae_Logic16/Firmware#FPGA_variables

This fixes bug #466.
---

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index ac53cee8..bf71ea60 100644
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -499,8 +499,8 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
 		return ret;
 
 	if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
-		sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1);
-		return SR_ERR;
+		sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. "
+		       "Proceeding anyway.", reg1);
 	}
 
 	if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK)