From: Bert Vermeulen Date: Fri, 16 May 2014 21:04:14 +0000 (+0200) Subject: fx2lafw: Basic acquisition support for DSLogic. X-Git-Tag: libsigrok-0.4.0~603 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=b9d530920fa97ab92d5f78f6f00a1ffc73259f2f;p=libsigrok.git fx2lafw: Basic acquisition support for DSLogic. --- diff --git a/Makefile.am b/Makefile.am index 9ea9788c..2f56b49a 100644 --- a/Makefile.am +++ b/Makefile.am @@ -225,7 +225,8 @@ libsigrok_la_SOURCES += \ src/hardware/fx2lafw/protocol.h \ src/hardware/fx2lafw/protocol.c \ src/hardware/fx2lafw/api.c \ - src/hardware/fx2lafw/dslogic.c + src/hardware/fx2lafw/dslogic.c \ + src/hardware/fx2lafw/dslogic.h endif if HW_GMC_MH_1X_2X libsigrok_la_SOURCES += \ diff --git a/hardware/fx2lafw/dslogic.c b/hardware/fx2lafw/dslogic.c deleted file mode 100644 index 714d4415..00000000 --- a/hardware/fx2lafw/dslogic.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the libsigrok project. - * - * Copyright (C) 2013 Bert Vermeulen - * Copyright (C) 2012 Joel Holdsworth - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include "protocol.h" - -#define FW_BUFSIZE 4096 -int dslogic_fpga_firmware_upload(struct libusb_device_handle *hdl, - const char *filename) -{ - FILE *fw; - struct stat st; - int chunksize, result, ret; - unsigned char *buf; - int sum, transferred; - - sr_info("Uploading FPGA firmware at %s.", filename); - - if (stat(filename, &st) < 0) { - sr_err("Unable to upload FPGA firmware: %s", strerror(errno)); - return SR_ERR; - } - - /* Tell the device firmware is coming. */ - if ((ret = libusb_control_transfer(hdl, LIBUSB_REQUEST_TYPE_VENDOR | - LIBUSB_ENDPOINT_OUT, CMD_DSLOGIC_CONFIG, 0x0000, 0x0000, - NULL, 0, 3000)) < 0) { - sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); - return SR_ERR; - } - buf = g_malloc(FW_BUFSIZE); - - if ((fw = g_fopen(filename, "rb")) == NULL) { - sr_err("Unable to open %s for reading: %s.", filename, strerror(errno)); - return SR_ERR; - } - - /* Give the FX2 time to get ready for FPGA firmware upload. */ - g_usleep(10 * 1000); - - sum = 0; - result = SR_OK; - while (1) { - if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0) - break; - - if ((ret = libusb_bulk_transfer(hdl, 2 | LIBUSB_ENDPOINT_OUT, - buf, chunksize, &transferred, 1000)) < 0) { - sr_err("Unable to configure FPGA firmware: %s.", - libusb_error_name(ret)); - result = SR_ERR; - break; - } - sum += transferred; - sr_info("Uploaded %d/%d bytes.", sum, st.st_size); - - if (transferred != chunksize) { - sr_err("Short transfer while uploading FPGA firmware."); - result = SR_ERR; - break; - } - } - fclose(fw); - if (result == SR_OK) - sr_info("FPGA firmware upload done."); - - return result; -} - diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c index ccd769b2..1e6d4011 100644 --- a/src/hardware/fx2lafw/api.c +++ b/src/hardware/fx2lafw/api.c @@ -19,6 +19,7 @@ */ #include "protocol.h" +#include "dslogic.h" static const struct fx2lafw_profile supported_fx2[] = { /* @@ -411,7 +412,7 @@ static int dev_open(struct sr_dev_inst *sdi) } if (devc->dslogic) { - if ((ret = dslogic_fpga_firmware_upload(usb->devhdl, + if ((ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE)) != SR_OK) return ret; } @@ -611,22 +612,17 @@ static int receive_data(int fd, int revents, void *cb_data) return TRUE; } -static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) +static int start_transfers(const struct sr_dev_inst *sdi) { struct dev_context *devc; - struct drv_context *drvc; struct sr_usb_dev_inst *usb; struct sr_trigger *trigger; struct libusb_transfer *transfer; - unsigned int i, timeout, num_transfers; - int ret; + unsigned int i, num_transfers; + int endpoint, timeout, ret; unsigned char *buf; size_t size; - if (sdi->status != SR_ST_ACTIVE) - return SR_ERR_DEV_CLOSED; - - drvc = di->priv; devc = sdi->priv; usb = sdi->conn; @@ -647,6 +643,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) devc->trigger_fired = TRUE; timeout = fx2lafw_get_timeout(devc); + num_transfers = fx2lafw_get_number_of_transfers(devc); size = fx2lafw_get_buffer_size(devc); devc->submitted_transfers = 0; @@ -657,6 +654,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) return SR_ERR_MALLOC; } + timeout = fx2lafw_get_timeout(devc); + endpoint = devc->dslogic ? 6 : 2; devc->num_transfers = num_transfers; for (i = 0; i < num_transfers; i++) { if (!(buf = g_try_malloc(size))) { @@ -665,7 +664,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) } transfer = libusb_alloc_transfer(0); libusb_fill_bulk_transfer(transfer, usb->devhdl, - 2 | LIBUSB_ENDPOINT_IN, buf, size, + endpoint | LIBUSB_ENDPOINT_IN, buf, size, fx2lafw_receive_transfer, (void *)sdi, timeout); if ((ret = libusb_submit_transfer(transfer)) != 0) { sr_err("Failed to submit transfer: %s.", @@ -679,16 +678,101 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) devc->submitted_transfers++; } - devc->ctx = drvc->sr_ctx; + /* Send header packet to the session bus. */ + std_session_send_df_header(devc->cb_data, LOG_PREFIX); usb_source_add(sdi->session, devc->ctx, timeout, receive_data, NULL); - /* Send header packet to the session bus. */ - std_session_send_df_header(cb_data, LOG_PREFIX); + return SR_OK; +} + +static void dslogic_trigger_receive(struct libusb_transfer *transfer) +{ + const struct sr_dev_inst *sdi; + struct dslogic_trigger_pos *tpos; + + sdi = transfer->user_data; + + if (transfer->status == LIBUSB_TRANSFER_COMPLETED + && transfer->actual_length == sizeof(struct dslogic_trigger_pos)) { + tpos = (struct dslogic_trigger_pos *)transfer->buffer; + sr_dbg("tpos real_pos %.8x ram_saddr %.8x", tpos->real_pos, tpos->ram_saddr); + g_free(tpos); + start_transfers(sdi); + } + + libusb_free_transfer(transfer); + +} + +static int dslogic_trigger_request(const struct sr_dev_inst *sdi) +{ + struct sr_usb_dev_inst *usb; + struct libusb_transfer *transfer; + struct dslogic_trigger_pos *tpos; + int ret; + + usb = sdi->conn; + + if ((ret = dslogic_stop_acquisition(sdi)) != SR_OK) + return ret; + + if ((ret = dslogic_fpga_configure(sdi)) != SR_OK) + return ret; - if ((ret = fx2lafw_command_start_acquisition(sdi)) != SR_OK) { - fx2lafw_abort_acquisition(devc); + if ((ret = dslogic_start_acquisition(sdi)) != SR_OK) return ret; + + sr_dbg("Getting trigger."); + tpos = g_malloc(sizeof(struct dslogic_trigger_pos)); + transfer = libusb_alloc_transfer(0); + libusb_fill_bulk_transfer(transfer, usb->devhdl, 6 | LIBUSB_ENDPOINT_IN, + (unsigned char *)tpos, sizeof(struct dslogic_trigger_pos), + dslogic_trigger_receive, (void *)sdi, 0); + if ((ret = libusb_submit_transfer(transfer)) < 0) { + sr_err("Failed to request trigger: %s.", libusb_error_name(ret)); + libusb_free_transfer(transfer); + g_free(tpos); + return SR_ERR; + } + + return ret; +} + +static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) +{ + struct drv_context *drvc; + struct dev_context *devc; + int timeout, ret; + + if (sdi->status != SR_ST_ACTIVE) + return SR_ERR_DEV_CLOSED; + + drvc = di->priv; + devc = sdi->priv; + + /* Configures devc->trigger_* and devc->sample_wide */ + if (fx2lafw_configure_channels(sdi) != SR_OK) { + sr_err("Failed to configure channels."); + return SR_ERR; + } + + devc->ctx = drvc->sr_ctx; + devc->cb_data = cb_data; + devc->sent_samples = 0; + devc->empty_transfer_count = 0; + devc->acq_aborted = FALSE; + + timeout = fx2lafw_get_timeout(devc); + usb_source_add(devc->ctx, timeout, receive_data, NULL); + + if (devc->dslogic) { + dslogic_trigger_request(sdi); + } + else { + if ((ret = fx2lafw_command_start_acquisition(sdi)) != SR_OK) + return ret; + start_transfers(sdi); } return SR_OK; diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c new file mode 100644 index 00000000..489671f5 --- /dev/null +++ b/src/hardware/fx2lafw/dslogic.c @@ -0,0 +1,229 @@ +/* + * This file is part of the libsigrok project. + * + * Copyright (C) 2013 Bert Vermeulen + * Copyright (C) 2012 Joel Holdsworth + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include "protocol.h" +#include "dslogic.h" + +#define FW_BUFSIZE 4096 +int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, + const char *filename) +{ + FILE *fw; + struct stat st; + struct sr_usb_dev_inst *usb; + int chunksize, result, ret; + unsigned char *buf; + int sum, transferred; + + sr_dbg("Uploading FPGA firmware at %s.", filename); + + usb = sdi->conn; + if (stat(filename, &st) < 0) { + sr_err("Unable to upload FPGA firmware: %s", strerror(errno)); + return SR_ERR; + } + + /* Tell the device firmware is coming. */ + if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | + LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000, + NULL, 0, 3000)) < 0) { + sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret)); + return SR_ERR; + } + buf = g_malloc(FW_BUFSIZE); + + if ((fw = g_fopen(filename, "rb")) == NULL) { + sr_err("Unable to open %s for reading: %s.", filename, strerror(errno)); + return SR_ERR; + } + + /* Give the FX2 time to get ready for FPGA firmware upload. */ + g_usleep(10 * 1000); + + sum = 0; + result = SR_OK; + while (1) { + if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0) + break; + + if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, + buf, chunksize, &transferred, 1000)) < 0) { + sr_err("Unable to configure FPGA firmware: %s.", + libusb_error_name(ret)); + result = SR_ERR; + break; + } + sum += transferred; + sr_spew("Uploaded %d/%d bytes.", sum, st.st_size); + + if (transferred != chunksize) { + sr_err("Short transfer while uploading FPGA firmware."); + result = SR_ERR; + break; + } + } + fclose(fw); + g_free(buf); + if (result == SR_OK) + sr_dbg("FPGA firmware upload done."); + + return result; +} + +int dslogic_start_acquisition(const struct sr_dev_inst *sdi) +{ + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + struct dslogic_mode mode; + int ret; + + devc = sdi->priv; + mode.flags = 0; + mode.sample_delay_h = mode.sample_delay_l = 0; + if (devc->sample_wide) + mode.flags |= DS_START_FLAGS_SAMPLE_WIDE; + + usb = sdi->conn; + ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | + LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, + (unsigned char *)&mode, sizeof(mode), 3000); + if (ret < 0) { + sr_err("Failed to send start command: %s.", libusb_error_name(ret)); + return SR_ERR; + } + + return SR_OK; +} + +int dslogic_stop_acquisition(const struct sr_dev_inst *sdi) +{ + struct sr_usb_dev_inst *usb; + struct dslogic_mode mode; + int ret; + + mode.flags = DS_START_FLAGS_STOP; + mode.sample_delay_h = mode.sample_delay_l = 0; + + usb = sdi->conn; + ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | + LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000, + (unsigned char *)&mode, sizeof(struct dslogic_mode), 3000); + if (ret < 0) { + sr_err("Failed to send stop command: %s.", libusb_error_name(ret)); + return SR_ERR; + } + + return SR_OK; +} + +int dslogic_fpga_configure(const struct sr_dev_inst *sdi) +{ + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + uint8_t c[3]; + struct dslogic_fpga_config cfg; + uint16_t v16; + uint32_t v32; + int transferred, len, ret; + + sr_dbg("Configuring FPGA."); + usb = sdi->conn; + devc = sdi->priv; + + WL32(&cfg.sync, DS_CFG_START); + WL16(&cfg.mode_header, DS_CFG_MODE); + WL32(&cfg.divider_header, DS_CFG_DIVIDER); + WL32(&cfg.count_header, DS_CFG_COUNT); + WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS); + WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); + WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP); + WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA); + WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0); + WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1); + WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0); + WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1); + WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0); + WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1); + WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0); + WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1); + WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0); + WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1); + WL32(&cfg.end_sync, DS_CFG_END); + + /* Pass in the length of a fixed-size struct. Really. */ + len = sizeof(struct dslogic_fpga_config) / 2; + c[0] = len & 0xff; + c[1] = (len >> 8) & 0xff; + c[2] = (len >> 16) & 0xff; + + ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | + LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, + c, 3, 100); + if (ret < 0) { + sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret)); + return SR_ERR; + } + + /* + * 15 1 = internal test mode + * 14 1 = external test mode + * 13 1 = loopback test mode + * 8-12 unused + * 7 1 = analog mode + * 6 1 = samplerate 400MHz + * 5 1 = samplerate 200MHz or analog mode + * 4 0 = logic, 1 = dso or analog + * 2-3 unused + * 1 0 = internal clock, 1 = external clock + * 0 1 = trigger enabled + */ + v16 = 0x0000; + if (devc->dslogic_mode == DS_OP_INTERNAL_TEST) + v16 = 1 << 15; + else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST) + v16 = 1 << 14; + else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST) + v16 = 1 << 13; + if (devc->dslogic_external_clock) + v16 |= 1 << 2; + WL16(&cfg.mode, v16); + + v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate); + WL32(&cfg.divider, v32); + WL32(&cfg.count, devc->limit_samples); + + len = sizeof(struct dslogic_fpga_config); + ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT, + (unsigned char *)&cfg, len, + &transferred, 100); + if (ret < 0 || transferred != len) { + sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret)); + return SR_ERR; + } + + return SR_OK; +} diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h new file mode 100644 index 00000000..4070eea7 --- /dev/null +++ b/src/hardware/fx2lafw/dslogic.h @@ -0,0 +1,128 @@ +/* + * This file is part of the libsigrok project. + * + * Copyright (C) 2013 Bert Vermeulen + * Copyright (C) 2012 Joel Holdsworth + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Modified protocol commands & flags used by DSLogic */ +#define DS_CMD_GET_FW_VERSION 0xb0 +#define DS_CMD_GET_REVID_VERSION 0xb1 +#define DS_CMD_START 0xb2 +#define DS_CMD_FPGA_FW 0xb3 +#define DS_CMD_CONFIG 0xb4 + +#define DS_NUM_TRIGGER_STAGES 16 +#define DS_START_FLAGS_STOP (1 << 7) +#define DS_START_FLAGS_CLK_48MHZ (1 << 6) +#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5) + +enum dslogic_operation_modes { + DS_OP_NORMAL, + DS_OP_INTERNAL_TEST, + DS_OP_EXTERNAL_TEST, + DS_OP_LOOPBACK_TEST, +}; + +struct dslogic_version { + uint8_t major; + uint8_t minor; +}; + +struct dslogic_mode { + uint8_t flags; + uint8_t sample_delay_h; + uint8_t sample_delay_l; +}; + +struct dslogic_trigger_pos { + uint32_t real_pos; + uint32_t ram_saddr; + uint8_t first_block[504]; +}; + +/* + * The FPGA is configured with TLV tuples. Length is specified as the + * number of 16-bit words, and the (type, length) header is in some + * cases padded with 0xffff. + */ +#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt) +#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff) +#define DS_CFG_START 0xffffffff +#define DS_CFG_MODE _DS_CFG(0, 1) +#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2) +#define DS_CFG_COUNT _DS_CFG_PAD(3, 2) +#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2) +#define DS_CFG_TRIG_GLB _DS_CFG(7, 1) +#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2) +#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2) +#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16) +#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16) +#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16) +#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16) +#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16) +#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16) +#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16) +#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16) +#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16) +#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16) +#define DS_CFG_END 0x00000000 + +struct dslogic_fpga_config { + uint32_t sync; + uint16_t mode_header; + uint16_t mode; + uint32_t divider_header; + uint32_t divider; + uint32_t count_header; + uint32_t count; + uint32_t trig_pos_header; + uint32_t trig_pos; + uint16_t trig_glb_header; + uint16_t trig_glb; + uint32_t trig_adp_header; + uint32_t trig_adp; + uint32_t trig_sda_header; + uint32_t trig_sda; + uint32_t trig_mask0_header; + uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_mask1_header; + uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_value0_header; + uint16_t trig_value0[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_value1_header; + uint16_t trig_value1[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_edge0_header; + uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_edge1_header; + uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_count0_header; + uint16_t trig_count0[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_count1_header; + uint16_t trig_count1[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_logic0_header; + uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES]; + uint32_t trig_logic1_header; + uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES]; + uint32_t end_sync; +}; + + +int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, + const char *filename); +int dslogic_start_acquisition(const struct sr_dev_inst *sdi); +int dslogic_stop_acquisition(const struct sr_dev_inst *sdi); +int dslogic_fpga_configure(const struct sr_dev_inst *sdi); diff --git a/src/hardware/fx2lafw/protocol.c b/src/hardware/fx2lafw/protocol.c index 7c230f71..e12fd0bd 100644 --- a/src/hardware/fx2lafw/protocol.c +++ b/src/hardware/fx2lafw/protocol.c @@ -21,6 +21,7 @@ #include #include #include "protocol.h" +#include "dslogic.h" #pragma pack(push, 1) @@ -62,7 +63,7 @@ static int command_get_revid_version(struct sr_dev_inst *sdi, uint8_t *revid) libusb_device_handle *devhdl = usb->devhdl; int cmd, ret; - cmd = devc->dslogic ? CMD_DSLOGIC_GET_REVID_VERSION : CMD_GET_REVID_VERSION; + cmd = devc->dslogic ? DS_CMD_GET_REVID_VERSION : CMD_GET_REVID_VERSION; ret = libusb_control_transfer(devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, cmd, 0x0000, 0x0000, revid, 1, 100); @@ -107,7 +108,7 @@ SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi) delay = SR_MHZ(30) / samplerate - 1; } - sr_info("GPIF delay = %d, clocksource = %sMHz.", delay, + sr_dbg("GPIF delay = %d, clocksource = %sMHz.", delay, (cmd.flags & CMD_START_FLAGS_CLK_48MHZ) ? "48" : "30"); if (delay <= 0 || delay > MAX_SAMPLE_DELAY) { @@ -395,7 +396,7 @@ SR_PRIV void fx2lafw_receive_transfer(struct libusb_transfer *transfer) return; } - sr_info("receive_transfer(): status %d received %d bytes.", + sr_dbg("receive_transfer(): status %d received %d bytes.", transfer->status, transfer->actual_length); /* Save incoming transfer before reusing the transfer struct. */ diff --git a/src/hardware/fx2lafw/protocol.h b/src/hardware/fx2lafw/protocol.h index f8c2f3e2..3fbf15e0 100644 --- a/src/hardware/fx2lafw/protocol.h +++ b/src/hardware/fx2lafw/protocol.h @@ -67,15 +67,6 @@ #define CMD_START_FLAGS_CLK_30MHZ (0 << CMD_START_FLAGS_CLK_SRC_POS) #define CMD_START_FLAGS_CLK_48MHZ (1 << CMD_START_FLAGS_CLK_SRC_POS) -/* Modified protocol commands & flags used by DSLogic */ -#define CMD_DSLOGIC_GET_REVID_VERSION 0xb1 -#define CMD_DSLOGIC_START 0xb2 -#define CMD_DSLOGIC_CONFIG 0xb3 -#define CMD_DSLOGIC_SETTING 0xb4 - -#define CMD_START_FLAGS_DSLOGIC_STOP_POS 7 -#define CMD_START_FLAGS_DSLOGIC_STOP (1 << CMD_START_FLAGS_DSLOGIC_STOP_POS) - struct fx2lafw_profile { uint16_t vid; uint16_t pid; @@ -128,6 +119,8 @@ struct dev_context { /* Is this a DSLogic? */ gboolean dslogic; + uint16_t dslogic_mode; + int dslogic_external_clock; }; SR_PRIV int fx2lafw_command_start_acquisition(const struct sr_dev_inst *sdi); @@ -140,7 +133,4 @@ SR_PRIV void fx2lafw_receive_transfer(struct libusb_transfer *transfer); SR_PRIV size_t fx2lafw_get_buffer_size(struct dev_context *devc); SR_PRIV unsigned int fx2lafw_get_number_of_transfers(struct dev_context *devc); SR_PRIV unsigned int fx2lafw_get_timeout(struct dev_context *devc); - -int dslogic_fpga_firmware_upload(struct libusb_device_handle *hdl, - const char *filename); #endif