From: Diego Asanza Date: Sun, 8 May 2016 08:59:54 +0000 (+0200) Subject: dslogic: Add support for long captures at high samplerates. X-Git-Tag: libsigrok-0.5.0~406 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=a9a9bfaa6a388b288127b90d15bb9e82bbb35c2d;p=libsigrok.git dslogic: Add support for long captures at high samplerates. To capture more than 16MSamples the hardware run length encoding option must be enabled, or captured data present errors. RLE encoding/decoding is done in hardware. Data streamed to the USB interface is not encoded. This commit enables RLE encoding for captures longer than 16MSamples. Signed-off-by: Diego Asanza --- diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c index 619544f9..d5bb153e 100644 --- a/src/hardware/fx2lafw/dslogic.c +++ b/src/hardware/fx2lafw/dslogic.c @@ -337,7 +337,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) * 6 1 = samplerate 400MHz * 5 1 = samplerate 200MHz or analog mode * 4 0 = logic, 1 = dso or analog - * 3 unused + * 3 1 = RLE encoding (enable for more than 16 Megasamples) * 1-2 00 = internal clock, * 01 = external clock rising, * 11 = external clock falling @@ -358,6 +358,11 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) v16 |= 1 << 2; } } + if (devc->limit_samples > DS_MAX_LOGIC_DEPTH && !devc->dslogic_continuous_mode){ + /* enable rle for long captures. + Without this, captured data present errors. */ + v16 |= 1<< 3; + } WL16(&cfg.mode, v16); v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate); diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h index b6c6e7d5..6cb827d3 100644 --- a/src/hardware/fx2lafw/dslogic.h +++ b/src/hardware/fx2lafw/dslogic.h @@ -35,6 +35,9 @@ #define DS_START_FLAGS_SAMPLE_WIDE (1 << 5) #define DS_START_FLAGS_MODE_LA (1 << 4) +/* enable rle to capture more samples than this limit */ +#define DS_MAX_LOGIC_DEPTH 16000000 + enum dslogic_operation_modes { DS_OP_NORMAL, DS_OP_INTERNAL_TEST,