From: Gerhard Sittig <redacted>
Date: Sat, 9 May 2020 15:16:13 +0000 (+0200)
Subject: asix-sigma: sync FPGA register names with documentation
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=9fb4c6324dc05e909387c3db44d5a43d899c8641;p=libsigrok.git

asix-sigma: sync FPGA register names with documentation

Rename source code identifiers for FPGA registers to closer match the
vendor's documentation.
---

diff --git a/src/hardware/asix-sigma/api.c b/src/hardware/asix-sigma/api.c
index 40f6cd00..15c22252 100644
--- a/src/hardware/asix-sigma/api.c
+++ b/src/hardware/asix-sigma/api.c
@@ -412,12 +412,12 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 	}
 
 	/* Enter trigger programming mode. */
-	sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
+	sigma_set_register(WRITE_TRIGGER_SELECT2, 0x20, devc);
 
 	triggerselect = 0;
 	if (devc->cur_samplerate >= SR_MHZ(100)) {
 		/* 100 and 200 MHz mode. */
-		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
+		sigma_set_register(WRITE_TRIGGER_SELECT2, 0x81, devc);
 
 		/* Find which pin to trigger on from mask. */
 		for (triggerpin = 0; triggerpin < 8; triggerpin++)
@@ -451,7 +451,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 			     sizeof(struct triggerinout), devc);
 
 	/* Go back to normal mode. */
-	sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
+	sigma_set_register(WRITE_TRIGGER_SELECT2, triggerselect, devc);
 
 	/* Set clock select register. */
 	clockselect.async = 0;
diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c
index f18344d4..0e27f07a 100644
--- a/src/hardware/asix-sigma/protocol.c
+++ b/src/hardware/asix-sigma/protocol.c
@@ -250,13 +250,13 @@ SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *
 		if (lut->m1d[3] & bit)
 			tmp[1] |= 0x80;
 
-		sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
+		sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp),
 				     devc);
-		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
+		sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc);
 	}
 
 	/* Send the parameters */
-	sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
+	sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params,
 			     sizeof(lut->params), devc);
 
 	return SR_OK;
diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h
index 929c930c..a32ee15e 100644
--- a/src/hardware/asix-sigma/protocol.h
+++ b/src/hardware/asix-sigma/protocol.h
@@ -55,14 +55,14 @@ enum asix_device_type {
 
 enum sigma_write_register {
 	WRITE_CLOCK_SELECT	= 0,
-	WRITE_TRIGGER_SELECT0	= 1,
-	WRITE_TRIGGER_SELECT1	= 2,
+	WRITE_TRIGGER_SELECT	= 1,
+	WRITE_TRIGGER_SELECT2	= 2,
 	WRITE_MODE		= 3,
 	WRITE_MEMROW		= 4,
 	WRITE_POST_TRIGGER	= 5,
 	WRITE_TRIGGER_OPTION	= 6,
 	WRITE_PIN_VIEW		= 7,
-
+	/* Unassigned register locations. */
 	WRITE_TEST		= 15,
 };
 
@@ -79,8 +79,9 @@ enum sigma_read_register {
 	READ_PIN_CHANGE_HIGH	= 9,
 	READ_BLOCK_LAST_TS_LOW	= 10,
 	READ_BLOCK_LAST_TS_HIGH	= 11,
-	READ_PIN_VIEW		= 12,
-
+	READ_BLOCK_TS_OVERRUN	= 12,
+	READ_PIN_VIEW		= 13,
+	/* Unassigned register location. */
 	READ_TEST		= 15,
 };