From: Uwe Hermann <redacted>
Date: Wed, 11 Sep 2013 17:20:15 +0000 (+0200)
Subject: uart: Fix corner-case that can occur with LA triggers.
X-Git-Tag: libsigrokdecode-0.3.0~328
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=83be7b8384e0dc20b84de831e5922fb9c6d0762d;p=libsigrokdecode.git

uart: Fix corner-case that can occur with LA triggers.

Assume that the initial pin state is 1/high for the RX and TX lines.

This fixes the decode when an LA triggers on e.g. TX=low (the first
sample would be low in that case, so the falling edge for the start bit
would be missed by the decoder).
---

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index b10012a..cca8952 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -111,8 +111,8 @@ class Decoder(srd.Decoder):
         self.stopbit1 = [-1, -1]
         self.startsample = [-1, -1]
         self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
-        self.oldbit = [None, None]
-        self.oldpins = None
+        self.oldbit = [1, 1]
+        self.oldpins = [1, 1]
 
     def start(self, metadata):
         self.samplerate = metadata['samplerate']
@@ -268,14 +268,6 @@ class Decoder(srd.Decoder):
             #     continue
             self.oldpins, (rx, tx) = pins, pins
 
-            # First sample: Save RX/TX value.
-            if self.oldbit[RX] == None:
-                self.oldbit[RX] = rx
-                continue
-            if self.oldbit[TX] == None:
-                self.oldbit[TX] = tx
-                continue
-
             # State machine.
             for rxtx in (RX, TX):
                 signal = rx if (rxtx == RX) else tx