From: majekw Date: Sat, 1 Dec 2018 23:16:28 +0000 (+0100) Subject: Add YiXingDianZi MDSO firmware support. X-Git-Tag: sigrok-firmware-fx2lafw-0.1.7~7 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=7a4d2e556c911dcd4182369fb2fbbd8dc70bf4f3;p=sigrok-firmware-fx2lafw.git Add YiXingDianZi MDSO firmware support. --- diff --git a/Makefile.am b/Makefile.am index d3c98429..5ed7af7c 100644 --- a/Makefile.am +++ b/Makefile.am @@ -49,7 +49,8 @@ dirstamps = \ hw/sigrok-fx2-16ch/$(dirstamp) \ hw/hantek-6022be/$(dirstamp) \ hw/hantek-6022bl/$(dirstamp) \ - hw/sainsmart-dds120/$(dirstamp) + hw/sainsmart-dds120/$(dirstamp) \ + hw/yixingdianzi-mdso/$(dirstamp) # Final firmware files firmware_binaries = \ @@ -64,7 +65,8 @@ firmware_binaries = \ hw/sigrok-fx2-16ch/fx2lafw-sigrok-fx2-16ch.fw \ hw/hantek-6022be/fx2lafw-hantek-6022be.fw \ hw/hantek-6022bl/fx2lafw-hantek-6022bl.fw \ - hw/sainsmart-dds120/fx2lafw-sainsmart-dds120.fw + hw/sainsmart-dds120/fx2lafw-sainsmart-dds120.fw \ + hw/yixingdianzi-mdso/fx2lafw-yixingdianzi-mdso.fw fx2lafw_headers = \ include/command.h \ @@ -98,6 +100,10 @@ sainsmart_dds120_headers = $(scope_headers) sainsmart_dds120_sources = hw/sainsmart-dds120/fw.c sainsmart_dds120_objects = hw/sainsmart-dds120/fw.rel +yixingdianzi_mdso_headers = $(scope_headers) +yixingdianzi_mdso_sources = hw/yixingdianzi-mdso/fw.c +yixingdianzi_mdso_objects = hw/yixingdianzi-mdso/fw.rel + fx2lib_headers = \ fx2lib/include/autovector.h \ fx2lib/include/delay.h \ @@ -238,12 +244,13 @@ hw_sources = \ hw/sigrok-fx2-16ch/dscr.a51 \ hw/hantek-6022be/dscr.a51 \ hw/hantek-6022bl/dscr.a51 \ - hw/sainsmart-dds120/dscr.a51 + hw/sainsmart-dds120/dscr.a51 \ + hw/yixingdianzi-mdso/dscr.a51 firmwaredir = $(datadir)/sigrok-firmware firmware_DATA = $(firmware_binaries) -dist_noinst_DATA = $(fx2lafw_headers) $(fx2lafw_sources) $(hantek_6022be_headers) $(hantek_6022be_sources) $(hantek_6022bl_headers) $(hantek_6022bl_sources) $(sainsmart_dds120_sources) $(sainsmart_dds120_headers) $(fx2lib_headers) $(fx2lib_sources) $(fx2lib_ints_sources) $(hw_sources) +dist_noinst_DATA = $(fx2lafw_headers) $(fx2lafw_sources) $(hantek_6022be_headers) $(hantek_6022be_sources) $(hantek_6022bl_headers) $(hantek_6022bl_sources) $(sainsmart_dds120_sources) $(sainsmart_dds120_headers) $(yixingdianzi_mdso_sources) $(yixingdianzi_mdso_headers) $(fx2lib_headers) $(fx2lib_sources) $(fx2lib_ints_sources) $(hw_sources) dist_noinst_SCRIPTS = autogen.sh MOSTLYCLEANFILES = *.asm fx2lib/lib/*.asm hw/**/*.asm fx2lib/lib/*.lib fx2lib/lib/interrupts/*.asm fx2lib/lib/interrupts/*.lib @@ -311,6 +318,7 @@ hw/sigrok-fx2-16ch/dscr.rel: hw/sigrok-fx2-16ch/$(dirstamp) include/dscr.inc hw/hantek-6022be/dscr.rel: hw/hantek-6022be/$(dirstamp) include/dscr_scope.inc hw/hantek-6022bl/dscr.rel: hw/hantek-6022bl/$(dirstamp) include/dscr_scope.inc hw/sainsmart-dds120/dscr.rel: hw/sainsmart-dds120/$(dirstamp) include/dscr_scope.inc +hw/yixingdianzi-mdso/dscr.rel: hw/yixingdianzi-mdso/$(dirstamp) include/dscr_scope.inc # Create build subdirectories @@ -362,6 +370,9 @@ hw/hantek-6022bl/fx2lafw-hantek-6022bl.ihx: hw/hantek-6022bl/dscr.rel $(hantek_6 hw/sainsmart-dds120/fx2lafw-sainsmart-dds120.ihx: hw/sainsmart-dds120/dscr.rel $(sainsmart_dds120_objects) $(fx2lib_libs) $(AM_V_GEN)$(SDCC) -mmcs51 $(SDCC_LINK_FLAGS_SCOPE) -o $@ hw/sainsmart-dds120/dscr.rel $(sainsmart_dds120_objects) $(fx2lib_libs) +hw/yixingdianzi-mdso/fx2lafw-yixingdianzi-mdso.ihx: hw/yixingdianzi-mdso/dscr.rel $(yixingdianzi_mdso_objects) $(fx2lib_libs) + $(AM_V_GEN)$(SDCC) -mmcs51 $(SDCC_LINK_FLAGS_SCOPE) -o $@ hw/yixingdianzi-mdso/dscr.rel $(yixingdianzi_mdso_objects) $(fx2lib_libs) + .a51.rel: $(SF_V_SDAS)$(SDAS8051) -glos $(as_includes) $@ $< diff --git a/hw/yixingdianzi-mdso/dscr.a51 b/hw/yixingdianzi-mdso/dscr.a51 new file mode 100644 index 00000000..04a8108f --- /dev/null +++ b/hw/yixingdianzi-mdso/dscr.a51 @@ -0,0 +1,27 @@ +;; +;; This file is part of the sigrok-firmware-fx2lafw project. +;; +;; Copyright (C) 2016 Uwe Hermann +;; +;; This program is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2 of the License, or +;; (at your option) any later version. +;; +;; This program is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with this program; if not, see . +;; + +VID = 0x501d ; Manufacturer ID (0x1d50) +PID = 0x8e60 ; Product ID (0x608e) +VER = 0x0400 ; Product "version". 0x0004 == YiXingDianZi MDSO. + +.include "dscr_scope.inc" +string_descriptor_a 3,^"YiXingDianZi MDSO" +_dev_strings_end: + .dw 0x0000 diff --git a/hw/yixingdianzi-mdso/fw.c b/hw/yixingdianzi-mdso/fw.c new file mode 100644 index 00000000..f84c257e --- /dev/null +++ b/hw/yixingdianzi-mdso/fw.c @@ -0,0 +1,107 @@ +/* + * This file is part of the sigrok-firmware-fx2lafw project. + * + * Copyright (C) 2009 Ubixum, Inc. + * Copyright (C) 2015 Jochen Hoenicke + * Copyright (C) 2018 Marek Wodzinski + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include +#include +#include +#include +#include + +#define SET_ANALOG_MODE() + +#define SET_COUPLING(x) + +#define SET_CALIBRATION_PULSE(x) + +#define TOGGLE_CALIBRATION_PIN() + +#define LED_CLEAR() NOP +#define LED_GREEN() NOP +#define LED_RED() NOP + +#define TIMER2_VAL 500 + +/* CTLx pin index (IFCLK, ADC clock input). */ +#define CTL_BIT 0 + +#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */ + +static const struct samplerate_info samplerates[] = { + { 48, 0x80, 0, 3, 0, 0x00, 0xea }, + { 30, 0x80, 0, 3, 0, 0x00, 0xaa }, + { 24, 1, 0, 2, 1, OUT0, 0xca }, + { 16, 1, 1, 2, 0, OUT0, 0xca }, + { 12, 2, 1, 2, 0, OUT0, 0xca }, + { 8, 3, 2, 2, 0, OUT0, 0xca }, + { 4, 6, 5, 2, 0, OUT0, 0xca }, + { 2, 12, 11, 2, 0, OUT0, 0xca }, + { 1, 24, 23, 2, 0, OUT0, 0xca }, + { 50, 48, 47, 2, 0, OUT0, 0xca }, + { 20, 120, 119, 2, 0, OUT0, 0xca }, + { 10, 240, 239, 2, 0, OUT0, 0xca }, +}; + +/* + * This sets three bits for each channel, one channel at a time. + * For channel 0 we want to set bits 1, 2 & 3 + * For channel 1 we want to set bits 4, 5 & 6 + * + * We convert the input values that are strange due to original + * firmware code into the value of the three bits as follows: + * + * val -> bits + * 1 -> 010b + * 2 -> 001b + * 5 -> 000b + * 10(16) -> 011b + * + * The third bit is always zero since there are only four outputs connected + * from the 74HC4051 chip. + */ +static BOOL set_voltage(BYTE channel, BYTE val) +{ + BYTE bits, mask; + + switch (val) { + case 1: + bits = 0x24; + break; + case 2: + bits = 0x12; + break; + case 5: + bits = 0x00; + break; + case 10: /* For backward compatibility. */ + case 16: + bits = 0x36; + break; + default: + return FALSE; + } + + mask = (channel) ? 0x70 : 0x0e; + IOA = (IOA & ~mask) | (bits & mask); + + return TRUE; +} + +#include