From: Joel Holdsworth <redacted>
Date: Mon, 12 Jun 2017 22:46:31 +0000 (-0600)
Subject: dslogic: Added half and quater-mode flags
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=780c5e246689290c1e28ec270da42a6049bf30f2;p=libsigrok.git

dslogic: Added half and quater-mode flags
---

diff --git a/src/hardware/dslogic/dslogic.c b/src/hardware/dslogic/dslogic.c
index 4d466143..297af2b0 100644
--- a/src/hardware/dslogic/dslogic.c
+++ b/src/hardware/dslogic/dslogic.c
@@ -345,6 +345,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 		v16 = DS_MODE_EXT_TEST;
 	else if (devc->mode == DS_OP_LOOPBACK_TEST)
 		v16 = DS_MODE_LPB_TEST;
+
+	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
+		v16 |= DS_MODE_HALF_MODE;
+	else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
+		v16 |= DS_MODE_QUAR_MODE;
+
 	if (devc->continuous_mode)
 		v16 |= DS_MODE_STREAM_MODE;
 	if (devc->external_clock) {