From: Sebski123 Date: Tue, 4 Aug 2020 13:46:34 +0000 (+0200) Subject: max7219: Add dumps for MAX7219 chips X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=697bfeeb8405eae32d08a714f388e716bc41a0ad;p=sigrok-dumps.git max7219: Add dumps for MAX7219 chips --- diff --git a/spi/max7219/README b/spi/max7219/README index 001b00b..c3b5200 100644 --- a/spi/max7219/README +++ b/spi/max7219/README @@ -21,7 +21,7 @@ The logic analyzer used was a Saleae Logic clone (at 2MHz): 3 CLK -Data +max7219.sr ---- The capture was generated using PulseView. @@ -29,3 +29,16 @@ The capture was generated using PulseView. The chip was driven by an FTDI FT232H connected to USB, using a custom Perl program to drive the signals, including the intentional error cases. + + +max7219_4x_cascaded_chips.sr +---- + +MAX7219 settings: + Number of daisy-chained chips = 4 + +The capture was generated using PulseView. + +The chip was driven by an Arduino UNO connected to USB, using code from here: +https://github.com/Sebski123/MAX72xx-Sigrok/blob/master/Sigrok_max7219_test_data.ino +to drive the signals, including the intentional error cases. diff --git a/spi/max7219/max7219_4x_cascaded_chips.sr b/spi/max7219/max7219_4x_cascaded_chips.sr new file mode 100644 index 0000000..642737e Binary files /dev/null and b/spi/max7219/max7219_4x_cascaded_chips.sr differ