From: Uwe Hermann <redacted>
Date: Wed, 9 Oct 2013 16:59:30 +0000 (+0200)
Subject: tlc5620: Use annotation types.
X-Git-Tag: libsigrokdecode-0.3.0~270
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=5f4de613af7b95dd37c6df69efb1214c741fdd05;p=libsigrokdecode.git

tlc5620: Use annotation types.

This fixes parts of bug #168.
---

diff --git a/decoders/tlc5620/__init__.py b/decoders/tlc5620/__init__.py
index bd68377..6cf3401 100644
--- a/decoders/tlc5620/__init__.py
+++ b/decoders/tlc5620/__init__.py
@@ -20,11 +20,6 @@
 
 '''
 Texas Instruments TLC5620 protocol decoder.
-
-TODO: Description.
-
-Details:
-TODO
 '''
 
 from .pd import *
diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 10f8572..9ce9e94 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -48,8 +48,11 @@ class Decoder(srd.Decoder):
     ]
     options = {}
     annotations = [
-        ['Text', 'Human-readable text'],
-        ['Warnings', 'Human-readable warnings'],
+        ['dac_select', 'DAC select'],
+        ['gain', 'Gain'],
+        ['value', 'DAC value'],
+        ['data_latch', 'Data latch point'],
+        ['ldac_fall', 'LDAC falling edge'],
     ]
 
     def __init__(self, **kwargs):
@@ -76,21 +79,21 @@ class Decoder(srd.Decoder):
 
         self.gain = 1 + self.bits[2]
         self.put(self.ss_gain, self.es_gain, self.out_ann,
-                 [0, ['Gain: x%d' % self.gain]])
+                 [1, ['Gain: x%d' % self.gain]])
 
         s = "".join(str(i) for i in self.bits[3:])
         self.dac_value = int(s, 2)
         self.put(self.ss_value, self.es_value, self.out_ann,
-                 [0, ['DAC value: %d' % self.dac_value]])
+                 [2, ['DAC value: %d' % self.dac_value]])
 
     def handle_falling_edge_load(self):
         self.put(self.samplenum, self.samplenum, self.out_ann,
-                 [0, ['Setting %s value to %d (x%d gain)' % \
+                 [3, ['Setting %s value to %d (x%d gain)' % \
                  (self.dac_select, self.dac_value, self.gain)]])
 
     def handle_falling_edge_ldac(self):
         self.put(self.samplenum, self.samplenum, self.out_ann,
-                 [0, ['Falling edge on LDAC pin']])
+                 [4, ['Falling edge on LDAC pin']])
 
     def handle_new_dac_bit(self):
         self.bits.append(self.datapin)