From: Uwe Hermann Date: Sat, 1 Feb 2014 14:40:27 +0000 (+0100) Subject: spi: Improve probe names/descriptions a bit. X-Git-Tag: libsigrokdecode-0.3.0~129 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=49e8a4d6fe1ac4f5f9100cce5e01ea59305adeb4;p=libsigrokdecode.git spi: Improve probe names/descriptions a bit. --- diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 03a45da..e6e45c4 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -64,14 +64,12 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, ] optional_probes = [ - {'id': 'miso', 'name': 'MISO', - 'desc': 'SPI MISO line (master in, slave out)'}, - {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (master out, slave in)'}, - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, + {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, + {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, ] options = { 'cs_polarity': ['CS# polarity', 'active-low'],