From: Uwe Hermann <redacted>
Date: Sat, 31 Mar 2012 15:04:50 +0000 (+0200)
Subject: srd: Decoders: Fix/simplify samplenum usage.
X-Git-Tag: libsigrokdecode-0.1.0~10
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=4180cba9a51acd32f69f0f8628bb746ea3e12be6;p=libsigrokdecode.git

srd: Decoders: Fix/simplify samplenum usage.
---

diff --git a/decoders/dcf77/dcf77.py b/decoders/dcf77/dcf77.py
index d8b9d3b..573888f 100644
--- a/decoders/dcf77/dcf77.py
+++ b/decoders/dcf77/dcf77.py
@@ -199,9 +199,7 @@ class Decoder(srd.Decoder):
             raise Exception('Invalid DCF77 bit: %d' % c)
 
     def decode(self, ss, es, data):
-        for samplenum, (val) in data: # TODO: Handle optional PON.
-
-            self.samplenum += 1 # FIXME. Use samplenum. Off-by-one?
+        for (self.samplenum, (val)) in data: # TODO: Handle optional PON.
 
             if self.state == 'WAIT FOR RISING EDGE':
                 # Wait until the next rising edge occurs.
diff --git a/decoders/i2c/i2c.py b/decoders/i2c/i2c.py
index cc70e96..5f67d35 100644
--- a/decoders/i2c/i2c.py
+++ b/decoders/i2c/i2c.py
@@ -198,8 +198,7 @@ class Decoder(srd.Decoder):
         super(Decoder, self).put(self.startsample, self.samplenum, output_id, data)
 
     def decode(self, ss, es, data):
-        for samplenum, (scl, sda) in data:
-            self.samplenum = samplenum
+        for (self.samplenum, (scl, sda)) in data:
 
             # First sample: Save SCL/SDA value.
             if self.oldscl == None:
diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index a2ae86f..5e5e74e 100644
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -83,9 +83,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
-
-            self.samplenum += 1 # FIXME
+        for (self.samplenum, (miso, mosi, sck, cs)) in data:
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -106,7 +104,7 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
+                self.start_sample = self.samplenum
                 active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted:
diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 6c9fdee..a478c8e 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -265,10 +265,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either RX or TX could be omitted (optional probe).
-        for (samplenum, (rx, tx)) in data:
-
-            # TODO: Start counting at 0 or 1? Increase before or after?
-            self.samplenum += 1
+        for (self.samplenum, (rx, tx)) in data:
 
             # First sample: Save RX/TX value.
             if self.oldbit[RX] == None:
diff --git a/decoders/usb/usb.py b/decoders/usb/usb.py
index f024f49..07f7bc0 100644
--- a/decoders/usb/usb.py
+++ b/decoders/usb/usb.py
@@ -115,16 +115,14 @@ class Decoder(srd.Decoder):
 
         # Initialise decoder state.
         self.sym = 'J'
-        self.scount = 0
+        self.samplenum = 0
         self.packet = ''
 
     def report(self):
         pass
 
     def decode(self, ss, es, data):
-        for (samplenum, (dm, dp)) in data:
-
-            self.scount += 1
+        for (self.samplenum, (dm, dp)) in data:
 
             sym = syms[dp, dm]
 
@@ -132,16 +130,16 @@ class Decoder(srd.Decoder):
             if sym == self.sym:
                 continue
 
-            if self.scount == 1:
+            if self.samplenum == 1:
                 # We ignore single sample width pulses.
                 # I sometimes get these with the OLS.
                 self.sym = sym
-                self.scount = 0
+                self.samplenum = 0
                 continue
 
             # How many bits since the last transition?
             if self.packet != '' or self.sym != 'J':
-                bitcount = int((self.scount - 1) * 12000000 / self.samplerate)
+                bitcount = int((self.samplenum - 1) * 12000000 / self.samplerate)
             else:
                 bitcount = 0
 
@@ -153,7 +151,7 @@ class Decoder(srd.Decoder):
                 else:
                     # Longer than EOP, assume reset.
                     self.put(0, 0, self.out_ann, [0, ['RESET']])
-                self.scount = 0
+                self.samplenum = 0
                 self.sym = sym
                 self.packet = ''
                 continue
@@ -167,6 +165,6 @@ class Decoder(srd.Decoder):
             elif bitcount > 6:
                 self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']])
 
-            self.scount = 0
+            self.samplenum = 0
             self.sym = sym