From: Gerhard Sittig <redacted>
Date: Thu, 22 Oct 2020 17:27:06 +0000 (+0200)
Subject: input/vcd: fix a divide by zero bug in the analog-only case
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=2cb4204c6f31b58a4713ce39b77d37b95f0b20f5;p=libsigrok.git

input/vcd: fix a divide by zero bug in the analog-only case

When the input data exclusively contained analog data, then creation of
the submit buffer for logic data caused a division by zero. Fix the
create_feed() routine.
---

diff --git a/src/input/vcd.c b/src/input/vcd.c
index fb25f10a..4e0310ba 100644
--- a/src/input/vcd.c
+++ b/src/input/vcd.c
@@ -1096,9 +1096,11 @@ static void create_feeds(const struct sr_input *in)
 	inc = in->priv;
 
 	/* Create one feed for logic data. */
-	inc->unit_size = (inc->logic_count + 7) / 8;
-	inc->feed_logic = feed_queue_logic_alloc(in->sdi,
-		CHUNK_SIZE / inc->unit_size, inc->unit_size);
+	if (inc->logic_count) {
+		inc->unit_size = (inc->logic_count + 7) / 8;
+		inc->feed_logic = feed_queue_logic_alloc(in->sdi,
+			CHUNK_SIZE / inc->unit_size, inc->unit_size);
+	}
 
 	/* Create one feed per analog channel. */
 	for (l = inc->channels; l; l = l->next) {