From: Oleksij Rempel <redacted>
Date: Tue, 23 Aug 2016 16:41:48 +0000 (+0200)
Subject: spi/ssi32: add README with setup description
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=281603c3cef1d923b1c45cd05b95b58d1c3bebd1;p=sigrok-dumps.git

spi/ssi32: add README with setup description

Signed-off-by: Oleksij Rempel <redacted>
---

diff --git a/spi/ssi32/README b/spi/ssi32/README
new file mode 100644
index 0000000..e654b87
--- /dev/null
+++ b/spi/ssi32/README
@@ -0,0 +1,55 @@
+-------------------------------------------------------------------------------
+SPI / SSI32
+-------------------------------------------------------------------------------
+
+This is a set of SPI captures for the SSI32 protocol.
+
+
+Logic analyzer
+--------------
+
+The logic analyzer used was a DP Open Bench Logic Sniffer (with different
+sample rate configurations).
+
+
+Probing
+-------
+
+The sigrok command line used was:
+
+  sigrok-cli --driver=ols:conn=/dev/ttyACM0 --config samplerate=<srate> \
+             --time=100 -t 3=0 -C 0-4 -o <file>
+
+
+ssi32_bananapi_loop_test.sr, samplerate 5m
+------------------------------------------
+
+Created on Banana Pi with SPI clock = 1MHz. MISO connected in a loop to itself.
+
+Pins:
+
+  Banana Pi           LA        LOOP
+  ----------------------------------
+  (CON3) SPI-CLK ---> CLK  ---~ (NC)
+  (CON3) SPI-MISO <-- MISO <---
+  (CON3) SPI-MOSI --> MOSI -->^
+  (CON3) IO-4    <--- FC#  <---
+  (CON3) SPI-CE0 ---> CS#  -->^
+
+
+ssi32_watchdog.sr, samplerate 10m
+---------------------------------
+
+Created on Banana Pi attached to STM32F3 Discovery. SPI clock = 5MHz.
+STM32F3 was running ssi32_slave example with soft watchdog on LUN=9.
+
+Pins:
+
+  Banana Pi           LA         STM32F3 Discovery
+  ------------------------------------------------
+  (CON3) SPI-CLK ---> CLK  --->  (P2) PC10
+  (CON3) SPI-MISO <-- MISO <---  (P2) PC11
+  (CON3) SPI-MOSI --> MOSI --->  (P2) PC12
+  (CON3) SPI-CE0 ---> CS#  --->  (P3) PD12
+  (CON3) IO-4    <--- FC#  <---  (P2) PB4
+