From: Uwe Hermann Date: Tue, 8 Jul 2014 19:36:53 +0000 (+0200) Subject: Various PDs: Minor consistency fixes. X-Git-Tag: libsigrokdecode-0.4.0~206 X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=21b39043472eeeb2e0155eafc73247f5010af714;p=libsigrokdecode.git Various PDs: Minor consistency fixes. (Consistently use single-quotes for all Python strings everywhere) --- diff --git a/decoders/onewire_link/pd.py b/decoders/onewire_link/pd.py index 93cd51a..c8d6cd7 100644 --- a/decoders/onewire_link/pd.py +++ b/decoders/onewire_link/pd.py @@ -254,10 +254,10 @@ class Decoder(srd.Decoder): # Save the sample number for the rising edge. self.rise = self.samplenum self.putfr([2, ['Reset', 'Rst', 'R']]) - self.state = "WAIT FOR PRESENCE DETECT" + self.state = 'WAIT FOR PRESENCE DETECT' # Otherwise this is assumed to be a data bit. else: - self.state = "WAIT FOR FALLING EDGE" + self.state = 'WAIT FOR FALLING EDGE' elif self.state == 'WAIT FOR PRESENCE DETECT': # Sample presence status. t = self.samplenum - self.rise diff --git a/decoders/rgb_led_spi/pd.py b/decoders/rgb_led_spi/pd.py index 8577928..ca0b113 100644 --- a/decoders/rgb_led_spi/pd.py +++ b/decoders/rgb_led_spi/pd.py @@ -65,5 +65,5 @@ class Decoder(srd.Decoder): rgb_value |= int(blue) self.cmd_es = es - self.putx([0, ["#%.6x" % rgb_value]]) + self.putx([0, ['#%.6x' % rgb_value]]) self.mosi_bytes = [] diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py index f8c90d9..6e7c454 100644 --- a/decoders/tlc5620/pd.py +++ b/decoders/tlc5620/pd.py @@ -65,7 +65,7 @@ class Decoder(srd.Decoder): self.out_ann = self.register(srd.OUTPUT_ANN) def handle_11bits(self): - s = "".join(str(i) for i in self.bits[:2]) + s = ''.join(str(i) for i in self.bits[:2]) self.dac_select = s = dacs[int(s, 2)] self.put(self.ss_dac, self.es_dac, self.out_ann, [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, @@ -75,7 +75,7 @@ class Decoder(srd.Decoder): self.put(self.ss_gain, self.es_gain, self.out_ann, [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) - s = "".join(str(i) for i in self.bits[3:]) + s = ''.join(str(i) for i in self.bits[3:]) self.dac_value = v = int(s, 2) self.put(self.ss_value, self.es_value, self.out_ann, [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,