From: Uwe Hermann Date: Mon, 21 Dec 2015 14:07:09 +0000 (+0100) Subject: Move 1mhz_clock/ into misc/. X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=1cd115bfa6b37e5172dfc3687ea9b70b38430c05;p=sigrok-dumps.git Move 1mhz_clock/ into misc/. --- diff --git a/misc/1mhz_clock/1mhz_clock_16channels.sr b/misc/1mhz_clock/1mhz_clock_16channels.sr new file mode 100644 index 0000000..c9b5965 Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_16channels.sr differ diff --git a/misc/1mhz_clock/1mhz_clock_1channels.sr b/misc/1mhz_clock/1mhz_clock_1channels.sr new file mode 100644 index 0000000..0fdd10e Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_1channels.sr differ diff --git a/misc/1mhz_clock/1mhz_clock_4channels.sr b/misc/1mhz_clock/1mhz_clock_4channels.sr new file mode 100644 index 0000000..6cc3e06 Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_4channels.sr differ diff --git a/misc/1mhz_clock/1mhz_clock_7channels.sr b/misc/1mhz_clock/1mhz_clock_7channels.sr new file mode 100644 index 0000000..0c84367 Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_7channels.sr differ diff --git a/misc/1mhz_clock/1mhz_clock_8channels.sr b/misc/1mhz_clock/1mhz_clock_8channels.sr new file mode 100644 index 0000000..30f52fc Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_8channels.sr differ diff --git a/misc/1mhz_clock/1mhz_clock_9channels.sr b/misc/1mhz_clock/1mhz_clock_9channels.sr new file mode 100644 index 0000000..fc7504a Binary files /dev/null and b/misc/1mhz_clock/1mhz_clock_9channels.sr differ diff --git a/misc/1mhz_clock/README b/misc/1mhz_clock/README new file mode 100644 index 0000000..a715bca --- /dev/null +++ b/misc/1mhz_clock/README @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +1MHz clock signal +------------------------------------------------------------------------------- + +This is a set of example captures of a digital 1MHz clock signal (rectangle +signal) generated using a function generator, sampled using a logic analyzer. + + +Logic analyzer setup +-------------------- + +The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): + + Probe Signal + ----------------------------- + 1 1MHz clock signal + + +Data +---- + +The sigrok command line used was: + + sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ + -o -p XXXX + +XXXX specifies how many probes to sample/save: + + - 1 signal: -p 1 + - 4 signals: -p 1-4 + - 7 signals: -p 1-7 + - 8 signals: -p 1-8 + - 9 signals: -p 1-9 + - 16 signals: -p 1-16 + diff --git a/random/1mhz_clock/1mhz_clock_16channels.sr b/random/1mhz_clock/1mhz_clock_16channels.sr deleted file mode 100644 index c9b5965..0000000 Binary files a/random/1mhz_clock/1mhz_clock_16channels.sr and /dev/null differ diff --git a/random/1mhz_clock/1mhz_clock_1channels.sr b/random/1mhz_clock/1mhz_clock_1channels.sr deleted file mode 100644 index 0fdd10e..0000000 Binary files a/random/1mhz_clock/1mhz_clock_1channels.sr and /dev/null differ diff --git a/random/1mhz_clock/1mhz_clock_4channels.sr b/random/1mhz_clock/1mhz_clock_4channels.sr deleted file mode 100644 index 6cc3e06..0000000 Binary files a/random/1mhz_clock/1mhz_clock_4channels.sr and /dev/null differ diff --git a/random/1mhz_clock/1mhz_clock_7channels.sr b/random/1mhz_clock/1mhz_clock_7channels.sr deleted file mode 100644 index 0c84367..0000000 Binary files a/random/1mhz_clock/1mhz_clock_7channels.sr and /dev/null differ diff --git a/random/1mhz_clock/1mhz_clock_8channels.sr b/random/1mhz_clock/1mhz_clock_8channels.sr deleted file mode 100644 index 30f52fc..0000000 Binary files a/random/1mhz_clock/1mhz_clock_8channels.sr and /dev/null differ diff --git a/random/1mhz_clock/1mhz_clock_9channels.sr b/random/1mhz_clock/1mhz_clock_9channels.sr deleted file mode 100644 index fc7504a..0000000 Binary files a/random/1mhz_clock/1mhz_clock_9channels.sr and /dev/null differ diff --git a/random/1mhz_clock/README b/random/1mhz_clock/README deleted file mode 100644 index a715bca..0000000 --- a/random/1mhz_clock/README +++ /dev/null @@ -1,35 +0,0 @@ -------------------------------------------------------------------------------- -1MHz clock signal -------------------------------------------------------------------------------- - -This is a set of example captures of a digital 1MHz clock signal (rectangle -signal) generated using a function generator, sampled using a logic analyzer. - - -Logic analyzer setup --------------------- - -The logic analyzer used was a Braintechnology USB-LPS (at 12MHz): - - Probe Signal - ----------------------------- - 1 1MHz clock signal - - -Data ----- - -The sigrok command line used was: - - sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \ - -o -p XXXX - -XXXX specifies how many probes to sample/save: - - - 1 signal: -p 1 - - 4 signals: -p 1-4 - - 7 signals: -p 1-7 - - 8 signals: -p 1-8 - - 9 signals: -p 1-9 - - 16 signals: -p 1-16 -