From: Gerhard Sittig <redacted>
Date: Mon, 21 Feb 2022 20:43:16 +0000 (+0100)
Subject: kingst-la2016: zero pad FPGA bitstream to 4KiB boundaries
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=1c445e0854b729151accae1b49e5bfb90694c770;p=libsigrok.git

kingst-la2016: zero pad FPGA bitstream to 4KiB boundaries

The 2KiB padding worked for LA2016 but kept looking susipcious. Pad the
FPGA bitstream to 4KiB boundaries, which unbreaks LA5016 and still works
with LA2016.
---

diff --git a/src/hardware/kingst-la2016/protocol.h b/src/hardware/kingst-la2016/protocol.h
index 5d465d94..dd109244 100644
--- a/src/hardware/kingst-la2016/protocol.h
+++ b/src/hardware/kingst-la2016/protocol.h
@@ -67,7 +67,7 @@
  * The device expects some zero padding to follow the content of the
  * file which contains the FPGA bitstream. Specify the chunk size here.
  */
-#define LA2016_EP2_PADDING	2048
+#define LA2016_EP2_PADDING	4096
 
 /*
  * Whether the logic input threshold voltage is a config item of the