From: Gerhard Sittig <redacted>
Date: Mon, 18 May 2020 20:09:39 +0000 (+0200)
Subject: asix-sigma: more trigger LUT download rephrase, think 16bit entities
X-Git-Url: https://sigrok.org/gitaction?a=commitdiff_plain;h=1385f791b0a3705d2f45418cbb156e48840052c3;p=libsigrok.git

asix-sigma: more trigger LUT download rephrase, think 16bit entities

Further rephrase the sigma_write_trigger_lut() routine. It's helpful to
"think" in BE16 quantities to improve readability of LUT address and
parameter downloads. Better matches the vendor's documentation. Also use
a better name for the "trigger select 2" register content.
---

diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c
index edddb293..023001d9 100644
--- a/src/hardware/asix-sigma/protocol.c
+++ b/src/hardware/asix-sigma/protocol.c
@@ -435,8 +435,9 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
 	size_t lut_addr;
 	uint16_t bit;
 	uint8_t m3d, m2d, m1d, m0d;
-	uint8_t buf[6], *wrptr, v8;
-	uint16_t selreg;
+	uint8_t buf[6], *wrptr;
+	uint8_t trgsel2;
+	uint16_t lutreg, selreg;
 	int ret;
 
 	/*
@@ -497,15 +498,19 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
 		 * programming.
 		 */
 		wrptr = buf;
-		write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0));
-		write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0));
+		lutreg = 0;
+		lutreg <<= 4; lutreg |= m3d;
+		lutreg <<= 4; lutreg |= m2d;
+		lutreg <<= 4; lutreg |= m1d;
+		lutreg <<= 4; lutreg |= m0d;
+		write_u16be_inc(&wrptr, lutreg);
 		ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT,
 			buf, wrptr - buf);
 		if (ret != SR_OK)
 			return ret;
-		v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
+		trgsel2 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
 			(lut_addr & TRGSEL2_LUT_ADDR_MASK);
-		ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8);
+		ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trgsel2);
 		if (ret != SR_OK)
 			return ret;
 	}