ir_rc5: Rephrase open coded value for start bit 1

Make obvious that the start bit's value is 1 in the IDLE stage.

diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py
index ae29f1028fd2418541e5c4d331fc85164629cfd4..edb29bd2b66e20a74450f9368ce347168c4880fe 100644 (file)
--- a/decoders/ir_rc5/pd.py
+++ b/decoders/ir_rc5/pd.py
@@ -147,8 +147,9 @@ class Decoder(srd.Decoder):
 
             # State machine.
             if self.state == 'IDLE':
+                bit = 1
                 self.edges.append(self.samplenum)
-                self.bits.append([self.samplenum, 1])
+                self.bits.append([self.samplenum, bit])
                 self.state = 'MID1'
                 self.old_ir = self.ir
                 continue