hantek-4032l: Add support for external clocks.

These options are NOT available for FPGA version 0.

- add option to select edge type

Signed-off-by: Andrej Valek <redacted>

diff --git a/src/hardware/hantek-4032l/api.c b/src/hardware/hantek-4032l/api.c
index b2e6e5dc6cf8cc6478ebded8d7914ec5bf8f0ccb..c35c7a85bf1aa9d36011a19574dbac56c51ba7f1 100644 (file)
--- a/src/hardware/hantek-4032l/api.c
+++ b/src/hardware/hantek-4032l/api.c
@@ -39,12 +39,47 @@ static const uint32_t devopts[] = {
        SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
        SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
        SR_CONF_CONN | SR_CONF_GET,
+       SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+       SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+};
+
+static const uint32_t devopts_fpga_zero[] = {
+       SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
+       SR_CONF_CONN | SR_CONF_GET,
 };
 
 static const uint32_t devopts_cg[] = {
        SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 };
 
+static const char *signal_edges[] = {
+       [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
+       [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
+       [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
+};
+
+static const char *ext_clock_sources[] = {
+       [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
+       [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
+};
+
+static const uint8_t ext_clock_edges[2][3] = {
+       {
+               H4032L_CLOCK_EDGE_TYPE_RISE_A,
+               H4032L_CLOCK_EDGE_TYPE_FALL_A,
+               H4032L_CLOCK_EDGE_TYPE_BOTH_A
+       },
+       {
+               H4032L_CLOCK_EDGE_TYPE_RISE_B,
+               H4032L_CLOCK_EDGE_TYPE_FALL_B,
+               H4032L_CLOCK_EDGE_TYPE_BOTH_B
+       }
+};
+
 static const int32_t trigger_matches[] = {
        SR_TRIGGER_ZERO,
        SR_TRIGGER_ONE,
@@ -214,10 +249,14 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
                /* Initialize command packet. */
                devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
                devc->cmd_pkt.sample_size = 16384;
+               devc->sample_rate = 0;
 
                devc->status = H4032L_STATUS_IDLE;
 
                devc->capture_ratio = 5;
+               devc->external_clock = FALSE;
+               devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
+
                devc->cur_threshold[0] = 2.5;
                devc->cur_threshold[1] = 2.5;
 
@@ -297,6 +336,7 @@ static int config_get(uint32_t key, GVariant **data,
 {
        struct dev_context *devc = sdi->priv;
        struct sr_usb_dev_inst *usb;
+       unsigned int idx;
 
        switch (key) {
        case SR_CONF_VOLTAGE_THRESHOLD:
@@ -312,7 +352,7 @@ static int config_get(uint32_t key, GVariant **data,
                }
                break;
        case SR_CONF_SAMPLERATE:
-               *data = g_variant_new_uint64(samplerates_hw[devc->cmd_pkt.sample_rate]);
+               *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
                break;
        case SR_CONF_CAPTURE_RATIO:
                *data = g_variant_new_uint64(devc->capture_ratio);
@@ -320,11 +360,26 @@ static int config_get(uint32_t key, GVariant **data,
        case SR_CONF_LIMIT_SAMPLES:
                *data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
                break;
+       case SR_CONF_EXTERNAL_CLOCK:
+               *data = g_variant_new_boolean(devc->external_clock);
+               break;
+       case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+               idx = devc->external_clock_source;
+               if (idx >= ARRAY_SIZE(ext_clock_sources))
+                       return SR_ERR_BUG;
+               *data = g_variant_new_string(ext_clock_sources[idx]);
+               break;
        case SR_CONF_CONN:
                if (!sdi || !(usb = sdi->conn))
                        return SR_ERR_ARG;
                *data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
                break;
+       case SR_CONF_CLOCK_EDGE:
+               idx = devc->clock_edge;
+               if (idx >= ARRAY_SIZE(signal_edges))
+                       return SR_ERR_BUG;
+               *data = g_variant_new_string(signal_edges[idx]);
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -337,6 +392,7 @@ static int config_set(uint32_t key, GVariant *data,
 {
        struct dev_context *devc = sdi->priv;
        struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
+       int idx;
 
        switch (key) {
        case SR_CONF_SAMPLERATE: {
@@ -349,7 +405,7 @@ static int config_set(uint32_t key, GVariant *data,
                                sr_err("Invalid sample rate.");
                                return SR_ERR_SAMPLERATE;
                        }
-                       cmd_pkt->sample_rate = i;
+                       devc->sample_rate = i;
                        break;
                }
        case SR_CONF_CAPTURE_RATIO: {
@@ -388,6 +444,19 @@ static int config_set(uint32_t key, GVariant *data,
                        }
                        break;
                }
+       case SR_CONF_EXTERNAL_CLOCK:
+               devc->external_clock = g_variant_get_boolean(data);
+               break;
+       case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+               if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
+                       return SR_ERR_ARG;
+               devc->external_clock_source = idx;
+               break;
+       case SR_CONF_CLOCK_EDGE:
+               if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
+                       return SR_ERR_ARG;
+               devc->clock_edge = idx;
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -398,6 +467,9 @@ static int config_set(uint32_t key, GVariant *data,
 static int config_list(uint32_t key, GVariant **data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
+
+       struct dev_context *devc = (sdi) ? sdi->priv : NULL;
+
        switch (key) {
        case SR_CONF_SCAN_OPTIONS:
        case SR_CONF_DEVICE_OPTIONS:
@@ -405,6 +477,9 @@ static int config_list(uint32_t key, GVariant **data,
                        *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
                        break;
                }
+               /* Disable external clock and edges for FPGA version 0. */
+               if (devc && (!devc->fpga_version))
+                       return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
                return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
        case SR_CONF_SAMPLERATE:
                *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
@@ -418,6 +493,12 @@ static int config_list(uint32_t key, GVariant **data,
        case SR_CONF_LIMIT_SAMPLES:
                *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
                break;
+       case SR_CONF_CLOCK_EDGE:
+               *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
+               break;
+       case SR_CONF_EXTERNAL_CLOCK_SOURCE:
+               *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -442,6 +523,12 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
        cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
        devc->trigger_pos = cmd_pkt->pre_trigger_size;
 
+       /* Set clock edge, when external clock is enabled. */
+       if (devc->external_clock)
+               cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
+       else
+               cmd_pkt->sample_rate = devc->sample_rate;
+
        /* Set pwm channel values. */
        devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
        devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);

diff --git a/src/hardware/hantek-4032l/protocol.h b/src/hardware/hantek-4032l/protocol.h
index 8b75140a1b6758e70cc6e27ce558d13789e64d6f..6725983aa4cee102dea973a01984c813f76e227f 100644 (file)
--- a/src/hardware/hantek-4032l/protocol.h
+++ b/src/hardware/hantek-4032l/protocol.h
@@ -44,6 +44,26 @@
 #define H4032L_START_PACKET_MAGIC 0x2B1A027F
 #define H4032L_END_PACKET_MAGIC 0x4D3C037F
 
+enum h4032l_clock_edge_type {
+       H4032L_CLOCK_EDGE_TYPE_RISE,
+       H4032L_CLOCK_EDGE_TYPE_FALL,
+       H4032L_CLOCK_EDGE_TYPE_BOTH
+};
+
+enum h4032l_ext_clock_source {
+       H4032L_EXT_CLOCK_SOURCE_CHANNEL_A,
+       H4032L_EXT_CLOCK_SOURCE_CHANNEL_B
+};
+
+enum h4032l_clock_edge_type_channel {
+       H4032L_CLOCK_EDGE_TYPE_RISE_A = 0x24,
+       H4032L_CLOCK_EDGE_TYPE_RISE_B,
+       H4032L_CLOCK_EDGE_TYPE_BOTH_A,
+       H4032L_CLOCK_EDGE_TYPE_BOTH_B,
+       H4032L_CLOCK_EDGE_TYPE_FALL_A,
+       H4032L_CLOCK_EDGE_TYPE_FALL_B
+};
+
 enum h4032l_trigger_edge_type {
        H4032L_TRIGGER_EDGE_TYPE_RISE,
        H4032L_TRIGGER_EDGE_TYPE_FALL,
@@ -126,6 +146,7 @@ struct h4032l_cmd_pkt {
 
 struct dev_context {
        enum h4032l_status status;
+       uint64_t sample_rate;
        unsigned int sent_samples;
        int submitted_transfers;
        uint32_t remaining_samples;
@@ -136,6 +157,9 @@ struct dev_context {
        uint8_t buffer[512];
        uint64_t capture_ratio;
        uint32_t trigger_pos;
+       gboolean external_clock;
+       enum h4032l_ext_clock_source external_clock_source;
+       enum h4032l_clock_edge_type clock_edge;
        double cur_threshold[2];
        uint32_t fpga_version;
 };