#define RUNSTATE_TRGD_BIT (1UL << 2)
#define RUNSTATE_POST_BIT (1UL << 3)
+/* Properties related to the layout of capture data downloads. */
+#define NUM_PACKETS_IN_CHUNK 5
+#define TRANSFER_PACKET_LENGTH 16
+
static int ctrl_in(const struct sr_dev_inst *sdi,
uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
void *data, uint16_t wLength)
{
struct dev_context *devc;
struct sr_trigger *trigger;
- struct trigger_cfg cfg;
+ struct trigger_cfg {
+ uint32_t channels;
+ uint32_t enabled;
+ uint32_t level;
+ uint32_t high_or_falling;
+ } cfg;
GSList *stages;
GSList *channel;
struct sr_trigger_stage *stage1;
uint64_t memory_bits; /* RAM capacity in Gbit (1, 2, 4). */
};
-struct trigger_cfg {
- uint32_t channels;
- uint32_t enabled;
- uint32_t level;
- uint32_t high_or_falling;
-};
-
-struct capture_info {
- uint32_t n_rep_packets;
- uint32_t n_rep_packets_before_trigger;
- uint32_t write_pos;
-};
-
-#define NUM_PACKETS_IN_CHUNK 5
-#define TRANSFER_PACKET_LENGTH 16
-
struct dev_context {
uint16_t usb_pid;
char *mcu_firmware;
gboolean trigger_involved;
gboolean completion_seen;
gboolean download_finished;
- struct capture_info info;
+ struct capture_info {
+ uint32_t n_rep_packets;
+ uint32_t n_rep_packets_before_trigger;
+ uint32_t write_pos;
+ } info;
uint32_t n_transfer_packets_to_read; /* each with 5 acq packets */
uint32_t n_bytes_to_read;
uint32_t n_reps_until_trigger;