"CH8", "CH9", "CH10", "CH11", "CH12", "CH13", "CH14", "CH15",
};
+/*
+ * The hardware uses a (model dependent) 100/200/500MHz base clock and
+ * a 16bit divider (common across all models). The range from 10kHz to
+ * 100/200/500MHz should be applicable to all devices. High rates may
+ * suffer from coarse resolution (e.g. in the "500MHz div 2" case) and
+ * may not provide the desired 1/2/5 steps. This is not an issue now,
+ * the 500MHz model is not supported yet by this driver.
+ */
+
static const uint64_t samplerates_la2016[] = {
+ SR_KHZ(10),
SR_KHZ(20),
SR_KHZ(50),
SR_KHZ(100),
};
static const uint64_t samplerates_la1016[] = {
+ SR_KHZ(10),
SR_KHZ(20),
SR_KHZ(50),
SR_KHZ(100),
return SR_OK;
}
-static int configure_channels(const struct sr_dev_inst *sdi)
-{
- struct dev_context *devc;
- GSList *l;
- struct sr_channel *ch;
-
- devc = sdi->priv;
-
- devc->cur_channels = 0;
- for (l = sdi->channels; l; l = l->next) {
- ch = l->data;
- if (!ch->enabled)
- continue;
- devc->cur_channels |= 1UL << ch->index;
- }
-
- return SR_OK;
-}
-
static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
struct sr_dev_driver *di;
ctx = drvc->sr_ctx;;
devc = sdi->priv;
- if (configure_channels(sdi) != SR_OK) {
- sr_err("Cannot configure channels.");
- return SR_ERR;
- }
-
devc->convbuffer_size = LA2016_CONVBUFFER_SIZE;
devc->convbuffer = g_try_malloc(devc->convbuffer_size);
if (!devc->convbuffer) {
#define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream"
#define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream"
-/* Maximum device capabilities. May differ between models. */
-#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
-#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
-#define MAX_SAMPLE_DEPTH 10e9
-#define MAX_PWM_FREQ SR_MHZ(20)
-#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */
-
/*
* Default device configuration. Must be applicable to any of the
* supported devices (no model specific default values yet). Specific
#define LA2016_DFLT_SAMPLEDEPTH (5 * 1000 * 1000)
#define LA2016_DFLT_CAPT_RATIO 5 /* Capture ratio, in percent. */
-/* TODO
- * What is the origin and motivation of that 128Mi literal? What is its
- * unit? How does it relate to a device's hardware capabilities? How to
- * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value?
- * It cannot be sample count. Is it memory size in bytes perhaps?
- */
-#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024)
-
/* USB vendor class control requests, executed by the Cypress FX2 MCU. */
#define CMD_FPGA_ENABLE 0x10
#define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
return SR_OK;
}
+static uint16_t get_channels_mask(const struct sr_dev_inst *sdi)
+{
+ uint16_t channels;
+ GSList *l;
+ struct sr_channel *ch;
+
+ channels = 0;
+ for (l = sdi->channels; l; l = l->next) {
+ ch = l->data;
+ if (ch->type != SR_CHANNEL_LOGIC)
+ continue;
+ if (!ch->enabled)
+ continue;
+ channels |= 1UL << ch->index;
+ }
+
+ return channels;
+}
+
static int set_trigger_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
memset(&cfg, 0, sizeof(cfg));
- cfg.channels = devc->cur_channels;
+ cfg.channels = get_channels_mask(sdi);
if (trigger && trigger->stages) {
stages = trigger->stages;
if (devc->cur_samplerate > devc->max_samplerate) {
sr_err("Too high a sample rate: %" PRIu64 ".",
devc->cur_samplerate);
- return SR_ERR;
+ return SR_ERR_ARG;
+ }
+ if (devc->cur_samplerate < MIN_SAMPLE_RATE_LA2016) {
+ sr_err("Too low a sample rate: %" PRIu64 ".",
+ devc->cur_samplerate);
+ return SR_ERR_ARG;
}
clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate;
divider_u16 = (uint16_t)(clock_divisor + 0.5);
devc->cur_samplerate = devc->max_samplerate / divider_u16;
- if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
+ if (devc->limit_samples > LA2016_NUM_SAMPLES_MAX) {
sr_err("Too high a sample depth: %" PRIu64 ".",
devc->limit_samples);
return SR_ERR;
}
+ if (devc->limit_samples < LA2016_NUM_SAMPLES_MIN) {
+ sr_err("Too low a sample depth: %" PRIu64 ".",
+ devc->limit_samples);
+ return SR_ERR;
+ }
/*
* The acquisition configuration communicates "pre-trigger"
#define LA2016_THR_VOLTAGE_MIN 0.40
#define LA2016_THR_VOLTAGE_MAX 4.00
-#define LA2016_NUM_SAMPLES_MIN 256
-#define LA2016_NUM_SAMPLES_MAX (10UL * 1000 * 1000 * 1000)
+#define LA2016_NUM_SAMPLES_MIN (UINT64_C(256))
+#define LA2016_NUM_SAMPLES_MAX (UINT64_C(10 * 1000 * 1000 * 1000))
+
+/* Maximum device capabilities. May differ between models. */
+#define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200)
+#define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100)
+#define MIN_SAMPLE_RATE_LA2016 SR_KHZ(10)
+#define MAX_PWM_FREQ SR_MHZ(20)
+#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */
+
+/* TODO
+ * What is the origin and motivation of that 128Mi literal? What is its
+ * unit? How does it relate to a device's hardware capabilities? How to
+ * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value?
+ * It cannot be sample count. Is it memory size in bytes perhaps?
+ */
+#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024)
#define LA2016_NUM_PWMCH_MAX 2
uint64_t cur_samplerate;
uint64_t limit_samples;
uint64_t capture_ratio;
- uint16_t cur_channels;
/* Internal acquisition and download state. */
gboolean trigger_involved;