Add sample 1MHz clock signal dumps.

diff --git a/random/1mhz_clock/1mhz_clock_16channels.sr b/random/1mhz_clock/1mhz_clock_16channels.sr
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diff --git a/random/1mhz_clock/1mhz_clock_1channels.sr b/random/1mhz_clock/1mhz_clock_1channels.sr
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diff --git a/random/1mhz_clock/1mhz_clock_4channels.sr b/random/1mhz_clock/1mhz_clock_4channels.sr
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diff --git a/random/1mhz_clock/1mhz_clock_7channels.sr b/random/1mhz_clock/1mhz_clock_7channels.sr
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diff --git a/random/1mhz_clock/1mhz_clock_8channels.sr b/random/1mhz_clock/1mhz_clock_8channels.sr
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diff --git a/random/1mhz_clock/1mhz_clock_9channels.sr b/random/1mhz_clock/1mhz_clock_9channels.sr
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diff --git a/random/1mhz_clock/README b/random/1mhz_clock/README
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+-------------------------------------------------------------------------------
+1MHz clock signal
+-------------------------------------------------------------------------------
+
+This is a set of example captures of a digital 1MHz clock signal (rectangle
+signal) generated using a function generator, sampled using a logic analyzer.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Braintechnology USB-LPS (at 12MHz):
+
+  Probe       Signal
+  -----------------------------
+  1           1MHz clock signal
+
+
+Data
+----
+
+The sigrok command line used was:
+
+  sigrok-cli --driver fx2lafw -d samplerate=12mhz --time 1s \
+             -o <filename> -p XXXX
+
+XXXX specifies how many probes to sample/save:
+
+ - 1 signal:   -p 1
+ - 4 signals:  -p 1-4
+ - 7 signals:  -p 1-7
+ - 8 signals:  -p 1-8
+ - 9 signals:  -p 1-9
+ - 16 signals: -p 1-16
+