if not self.reached_bit(self.curbit):
continue
self.handle_bit(can_rx)
- else:
- raise Exception("Invalid state: %s" % self.state)
self.state = 'WAIT FOR RISING EDGE'
- else:
- raise Exception('Invalid state: %s' % self.state)
-
self.oldval = val
self.state = 'IDLE'
else:
pass # TODO?
- else:
- raise Exception('Invalid state: %s' % self.state)
)
def __init__(self, **kwargs):
- self.state = None
self.curslave = -1
self.curdirection = None
self.packets = [] # Local cache of I²C packets
self.putremote()
self.ss_bit = self.ss_start = self.samplenum
self.state = 'IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
self.old_ir = self.ir
if edge == 's':
self.state = 'MID0'
bit = 0 if edge == 's' else None
- else:
- raise Exception('Invalid state: %s' % self.state)
self.edges.append(self.samplenum)
if bit != None:
elif self.state == 'UPDATE-IR':
self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
-
def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
# Rising TCK edges always advance the state machine.
self.advance_state_machine(tms)
handle_reg(cmd, val)
if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO'
self.state = 'IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
else:
# self.putx([0, ['Ignoring: %s (data=%s)' % (cmd, databyte)]])
pass
- else:
- raise Exception('Invalid state: %s' % self.state)
self.handle_get_data(lad, lad_bits)
elif self.state == 'GET TAR2':
self.handle_get_tar2(lad, lad_bits)
- else:
- raise Exception('Invalid state: %s' % self.state)
self.putx([0, ['Temperature conversion status: 0x%02x' % val]])
elif self.state in [s.upper() for s in command.values()]:
self.putx([0, ['TODO \'%s\': 0x%02x' % (self.state, val)]])
- else:
- raise Exception('Invalid state: %s' % self.state)
self.handle_syscommon_msg(pdata)
elif self.state == 'HANDLE SYSREALTIME MSG':
self.handle_sysrealtime_msg(pdata)
- else:
- raise Exception('Invalid state: %s' % self.state)
self.putx([1, ['Temperature: %3.2f K' % kelvin]])
self.state = 'IGNORE START REPEAT'
self.data = []
- else:
- raise Exception('Invalid state: %s' % self.state)
self.state = 'IDLE'
else:
pass # TODO?
- else:
- raise Exception('Invalid state: %s' % self.state)
else:
# self.putx([14, ['Ignoring: %s (data=%s)' % (cmd, databyte)]])
pass
- else:
- raise Exception('Invalid state: %s' % self.state)
# Wait for next slot.
self.state = 'WAIT FOR FALLING EDGE'
- else:
- raise Exception('Invalid state: %s' % self.state)
if self.onewire_collect(8, val, ss, es) == 0:
return
self.putx([0, ['ROM error data: 0x%02x' % self.data]])
- else:
- raise Exception('Invalid state: %s' % self.state)
# Data collector.
def onewire_collect(self, length, val, ss, es):
self.handle_device_reply(rxtx, self.cmd[rxtx][:-2])
elif rxtx == TX:
self.handle_host_command(rxtx, self.cmd[rxtx][:-2])
- else:
- raise Exception('Invalid rxtx value: %d' % rxtx)
self.cmd[rxtx] = ''
self.oldpins = None
self.ss_item = self.es_item = None
self.first = True
- self.state = 'IDLE'
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
continue
self.oldpins = pins
- # State machine.
- if self.state == 'IDLE':
- if pins[0] not in (0, 1):
- self.handle_bits(pins[1:])
- else:
- self.find_clk_edge(pins[0], pins[1:])
+ if pins[0] not in (0, 1):
+ self.handle_bits(pins[1:])
else:
- raise Exception('Invalid state: %s' % self.state)
+ self.find_clk_edge(pins[0], pins[1:])
self.state = 'IDLE'
else:
pass # TODO?
- else:
- raise Exception('Invalid state: %s' % self.state)
handle_response(miso)
self.state = 'IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
self.get_parity_bit(rxtx, signal)
elif self.state[rxtx] == 'GET STOP BITS':
self.get_stop_bits(rxtx, signal)
- else:
- raise Exception('Invalid state: %s' % self.state[rxtx])
# Save current RX/TX values for the next round.
self.oldbit[rxtx] = signal
self.bits, self.state = [], 'WAIT FOR SOP'
else:
pass # TODO: Error
- else:
- raise Exception('Invalid state: %s' % self.state)
self.get_bit(sym)
elif self.state == 'GET EOP':
self.get_eop(sym)
- else:
- raise Exception('Invalid state: %s' % self.state)