#include <libusb.h>
#include <stdlib.h>
#include <string.h>
+#include <math.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"
#include "protocol.h"
static const int32_t hwcaps[] = {
SR_CONF_LOGIC_ANALYZER,
SR_CONF_SAMPLERATE,
+ SR_CONF_VOLTAGE_THRESHOLD,
/* These are really implemented in the driver, not the hardware. */
SR_CONF_LIMIT_SAMPLES,
NULL,
};
+static const struct {
+ enum voltage_range range;
+ gdouble low;
+ gdouble high;
+} volt_thresholds[] = {
+ { VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
+ { VOLTAGE_RANGE_5_V, 1.4, 3.6 },
+};
+
static const uint64_t samplerates[] = {
SR_KHZ(500),
SR_MHZ(1),
if (!(devc = g_try_malloc0(sizeof(struct dev_context))))
return NULL;
+ devc->selected_voltage_range = VOLTAGE_RANGE_18_33_V;
sdi->priv = devc;
drvc->instances = g_slist_append(drvc->instances, sdi);
devices = g_slist_append(devices, sdi);
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
+ GVariant *range[2];
char str[128];
int ret;
+ unsigned i;
ret = SR_OK;
switch (key) {
devc = sdi->priv;
*data = g_variant_new_uint64(devc->cur_samplerate);
break;
+ case SR_CONF_VOLTAGE_THRESHOLD:
+ if (!sdi)
+ return SR_ERR;
+ devc = sdi->priv;
+ ret = SR_ERR;
+ for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++)
+ if (devc->selected_voltage_range ==
+ volt_thresholds[i].range) {
+ range[0] = g_variant_new_double(volt_thresholds[i].low);
+ range[1] = g_variant_new_double(volt_thresholds[i].high);
+ *data = g_variant_new_tuple(range, 2);
+ ret = SR_OK;
+ break;
+ }
+ break;
default:
return SR_ERR_NA;
}
static int config_set(int key, GVariant *data, const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ gdouble low, high;
int ret;
+ unsigned i;
if (sdi->status != SR_ST_ACTIVE)
return SR_ERR_DEV_CLOSED;
case SR_CONF_LIMIT_SAMPLES:
devc->limit_samples = g_variant_get_uint64(data);
break;
+ case SR_CONF_VOLTAGE_THRESHOLD:
+ g_variant_get(data, "(dd)", &low, &high);
+ ret = SR_ERR_ARG;
+ for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
+ if (fabs(volt_thresholds[i].low - low) < 0.1 &&
+ fabs(volt_thresholds[i].high - high) < 0.1) {
+ devc->selected_voltage_range =
+ volt_thresholds[i].range;
+ ret = SR_OK;
+ break;
+ }
+ }
+ break;
default:
ret = SR_ERR_NA;
}
static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
{
- GVariant *gvar;
+ GVariant *gvar, *range[2];
GVariantBuilder gvb;
int ret;
+ unsigned i;
(void)sdi;
g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
*data = g_variant_builder_end(&gvb);
break;
+ case SR_CONF_VOLTAGE_THRESHOLD:
+ g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
+ for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
+ range[0] = g_variant_new_double(volt_thresholds[i].low);
+ range[1] = g_variant_new_double(volt_thresholds[i].high);
+ gvar = g_variant_new_tuple(range, 2);
+ g_variant_builder_add_value(&gvb, gvar);
+ }
+ *data = g_variant_builder_end(&gvb);
+ break;
default:
return SR_ERR_NA;
}
uint8_t clock_select, reg1, reg10;
uint64_t div;
int i, ret, nchan = 0;
+ struct dev_context *devc;
+
+ devc = sdi->priv;
if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
return SR_ERR;
}
+ if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
+ return ret;
+
if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
return ret;
if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
return ret;
- if ((ret = upload_fpga_bitstream(sdi, VOLTAGE_RANGE_18_33_V)) != SR_OK)
+ if ((ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range)) != SR_OK)
return ret;
return SR_OK;
"Hold min", NULL},
{SR_CONF_SPL_MEASUREMENT_RANGE, SR_T_UINT64_RANGE, "spl_meas_range",
"Sound pressure level measurement range", NULL},
+ {SR_CONF_VOLTAGE_THRESHOLD, SR_T_DOUBLE_RANGE, "voltage_threshold",
+ "Voltage threshold", NULL },
{SR_CONF_POWER_OFF, SR_T_BOOL, "power_off",
"Power off", NULL},
{SR_CONF_DATA_SOURCE, SR_T_CHAR, "data_source",