]> sigrok.org Git - libsigrok.git/commitdiff
saleae-logic16: Downgrade error during capture to a message.
authorTim Hatch <redacted>
Sun, 2 Nov 2014 23:29:38 +0000 (15:29 -0800)
committerUwe Hermann <redacted>
Sun, 23 Nov 2014 12:47:45 +0000 (13:47 +0100)
Some clone doesn't set this to the exact same value, and both bits in 0x48 are
marked as unknown at
http://sigrok.org/wiki/Saleae_Logic16/Firmware#FPGA_variables

This fixes bug #466.

src/hardware/saleae-logic16/protocol.c

index ac53cee88866553471003c6b011de0313f8604db..bf71ea60f432908fe08399fe10ca55e334a0a58e 100644 (file)
@@ -499,8 +499,8 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
                return ret;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1);
-               return SR_ERR;
+               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. "
+                      "Proceeding anyway.", reg1);
        }
 
        if ((ret = read_fpga_register(sdi, 10, &reg10)) != SR_OK)