srd: MX25Lxx05D: Fix inverted SRWD bit handling.

diff --git a/decoders/mx25lxx05d/mx25lxx05d.py b/decoders/mx25lxx05d/mx25lxx05d.py
index a5dab2ef39721f062855f36a0e0d39fe06af3378..1d41fd418dad3428b6f01e33869fe027ffd46c63 100644 (file)
--- a/decoders/mx25lxx05d/mx25lxx05d.py
+++ b/decoders/mx25lxx05d/mx25lxx05d.py
@@ -113,7 +113,7 @@ def decode_status_reg(data):
     ret += 'Device is %sin continuously program mode (CP mode).\n' % s
 
     # Bits[7:7]: SRWD (status register write disable)
-    s = '' if (data & (1 << 7)) else 'not '
+    s = 'not ' if (data & (1 << 7)) else ''
     ret += 'Status register writes are %sallowed.\n' % s
 
     return ret