Rename 2ch-16bit-16khz to 2ch-32bit-8khz.

https://github.com/sigrokproject/libsigrokdecode/pull/6#issuecomment-442025810

diff --git a/i2s/2ch-16bit-16khz/2ch-16bit-16khz-no-samplerate.sr b/i2s/2ch-16bit-16khz/2ch-16bit-16khz-no-samplerate.sr
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diff --git a/i2s/2ch-16bit-16khz/2ch-16bit-16khz.sr b/i2s/2ch-16bit-16khz/2ch-16bit-16khz.sr
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diff --git a/i2s/2ch-16bit-16khz/README b/i2s/2ch-16bit-16khz/README
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--- a/i2s/2ch-16bit-16khz/README
+++ /dev/null
@@ -1,18 +0,0 @@
--------------------------------------------------------------------------------
-I2S Master 2-channel 16-bit 16-kHz
--------------------------------------------------------------------------------
-
-This is an example of an I2S master playing a recording of the BBC
-shipping forecast through one channel, and the other channel disconnected.
-
-Logic analyzer setup
---------------------
-
-The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):
-
-  Probe       I2S pin
-  -------------------
-  0           Clock
-  1           Frame Select
-  2           Data
-

diff --git a/i2s/2ch-32bit-8khz/2ch-32bit-8khz-no-samplerate.sr b/i2s/2ch-32bit-8khz/2ch-32bit-8khz-no-samplerate.sr
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diff --git a/i2s/2ch-32bit-8khz/2ch-32bit-8khz.sr b/i2s/2ch-32bit-8khz/2ch-32bit-8khz.sr
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diff --git a/i2s/2ch-32bit-8khz/README b/i2s/2ch-32bit-8khz/README
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--- /dev/null
+++ b/i2s/2ch-32bit-8khz/README
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+I2S Master 2-channel 32-bit 8-kHz
+-------------------------------------------------------------------------------
+
+This is an example of an I2S master playing a recording of the BBC
+shipping forecast through one channel, and the other channel disconnected.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was an EE Electronics ESLA201A (at 12MHz):
+
+  Probe       I2S pin
+  -------------------
+  0           Clock
+  1           Frame Select
+  2           Data