srd: usb: Preliminary USB low-speed support.

Some of the differences of USB low-speed (compared to full-speed) are:

 - 1.5Mb/s datarate, not 12MBit/s.
 - The J and K states are swapped/inverted.

Note: This is work in progress, further changes may still be needed.

Add a 'signalling' option, which allows the user to select whether the
PD should decode using the low-speed or full-speed signalling protocol.
If unspecified, the default is full-speed.

diff --git a/decoders/usb/__init__.py b/decoders/usb/__init__.py
index a7204dbe497e8712760433edac5aacb9194781e0..1a16f8f9f93e10a037768ffcd5654457dd19646e 100644 (file)
--- a/decoders/usb/__init__.py
+++ b/decoders/usb/__init__.py
@@ -19,21 +19,39 @@
 ##
 
 '''
-USB (full-speed) protocol decoder.
+USB (low-speed and full-speed) protocol decoder.
 
-Full-speed USB signalling consists of two signal lines, both driven at 3.3V
+USB signalling consists of two signal lines, both driven at 3.3V
 logic levels. The signals are DP (D+) and DM (D-), and normally operate in
 differential mode.
-The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
+
+Low-speed: The state where DP=1,DM=0 is K, the state DP=0,DM=1 is J.
+Full-speed: The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
+
 A state SE0 is defined where DP=DM=0. This common mode signal is used to
-signal a reset or end of packet.
+signal a reset or end of packet. A state SE1 is defined where DP=DM=1.
 
 Data transmitted on the USB is encoded with NRZI. A transition from J to K
 or vice-versa indicates a logic 0, while no transition indicates a logic 1.
 If 6 ones are transmitted consecutively, a zero is inserted to force a
-transition. This is known as bit stuffing. Data is transferred at a rate
-of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit
-intervals long.
+transition. This is known as bit stuffing.
+
+Data is transferred at a rate of 1.5Mbit/s (low-speed) / 12Mbit/s (full-speed).
+
+The SE0 transmitted to signal an end-of-packet is two bit intervals long
+(low-speed: 1.25uS - 1.50uS, full-speed: 160ns - 175ns).
+
+Bit/byte ordering: Bits are sent onto the bus LSB-first. Multibyte fields
+are transmitted in little-endian order (i.e., LSB to MSB).
+
+SYNC field: All packets begin with a SYNC field (8 bits).
+
+Packet field format: Packets start with an SOP (Start Of Packet) delimiter
+that is part of the SYNC field, and end with an EOP (End Of Packet).
+
+PID: A PID (packet identifier) follows the SYNC field of every packet. A PID
+consists of a 4-bit packet type field, and a 4 bit check field.
+The check field is the one's complement of the packet type field.
 
 Protocol output format:
 TODO

diff --git a/decoders/usb/usb.py b/decoders/usb/usb.py
index 15b42a9ee5360e4b11763d2e27e3522a409f830d..641ffe0b28a3695d85118f367daf792c6e34b9a8 100644 (file)
--- a/decoders/usb/usb.py
+++ b/decoders/usb/usb.py
@@ -18,20 +18,21 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# USB (full-speed) protocol decoder
+# USB (low-speed and full-speed) protocol decoder
 
 import sigrokdecode as srd
 
-# Symbols (used as states of our state machine, too)
+# Full-speed symbols (used as states of our state machine, too).
+# Note: Low-speed J and K are inverted compared to the full-speed J and K!
 syms = {
-        # (<dp>, <dm>): <state>
+        # (<dp>, <dm>): <symbol/state>
         (0, 0): 'SE0',
         (1, 0): 'J',
         (0, 1): 'K',
         (1, 1): 'SE1',
 }
 
-# ...
+# Packet IDs
 pids = {
     '10000111': 'OUT',      # Tokens
     '10010110': 'IN',
@@ -45,6 +46,19 @@ pids = {
     '01101001': 'NYET',
 }
 
+def get_sym(signalling, dp, dm):
+    # Note: Low-speed J and K are inverted compared to the full-speed J and K!
+    if signalling == 'low-speed':
+        s = syms[dp, dm]
+        if s == 'J':
+            return 'K'
+        elif s == 'K':
+            return 'J'
+        else:
+            return s
+    elif signalling == 'full-speed':
+       return syms[dp, dm]
+
 def bitstr_to_num(bitstr):
     if not bitstr:
         return 0
@@ -76,6 +90,7 @@ def packet_decode(packet):
     else:
         data = packet[16:]
 
+    # The SYNC pattern for low-speed/full-speed is KJKJKJKK (0001).
     if sync != '00000001':
         return 'SYNC INVALID!'
 
@@ -85,8 +100,8 @@ class Decoder(srd.Decoder):
     api_version = 1
     id = 'usb'
     name = 'USB'
-    longname = 'Universal Serial Bus'
-    desc = 'USB 1.x (full-speed) serial protocol.'
+    longname = 'Universal Serial Bus (LS/FS)'
+    desc = 'USB 1.x (low-speed and full-speed) serial protocol.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb']
@@ -95,7 +110,9 @@ class Decoder(srd.Decoder):
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
     ]
     optional_probes = []
-    options = {}
+    options = {
+        'signalling': ['Signalling', 'full-speed'],
+    }
     annotations = [
         ['Text', 'Human-readable text']
     ]
@@ -109,10 +126,6 @@ class Decoder(srd.Decoder):
     def start(self, metadata):
         self.samplerate = metadata['samplerate']
 
-        if self.samplerate < 48000000:
-            raise Exception('Samplerate (%d) not sufficient for USB '
-                            'decoding, need at least 48MHz' % self.samplerate)
-
         # self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
 
@@ -127,7 +140,7 @@ class Decoder(srd.Decoder):
             # last change in the D+/D- lines.
             self.scount += 1
 
-            sym = syms[dp, dm]
+            sym = get_sym(self.options['signalling'], dp, dm)
 
             # Wait for a symbol change (i.e., change in D+/D- lines).
             if sym == self.sym:
@@ -142,7 +155,11 @@ class Decoder(srd.Decoder):
 
             # How many bits since the last transition?
             if self.packet != '' or self.sym != 'J':
-                bitcount = int((self.scount - 1) * 12000000 / self.samplerate)
+                if self.options['signalling'] == 'low-speed':
+                    bitrate = 1500000 # 1.5Mb/s (+/- 1.5%)
+                elif self.options['signalling'] == 'full-speed':
+                    bitrate = 12000000 # 12Mb/s (+/- 0.25%)
+                bitcount = int((self.scount - 1) * bitrate / self.samplerate)
             else:
                 bitcount = 0