uart: Fix a bug in the output for stacked PDs.

The UART bit information was not transmitted correctly to stacked PDs
if there was an overlap between RX and TX bytes in the data.

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 0e6e548cfc08aa3ccc5a50981daa66e4c441d2aa..151cae424fefefde3774dd2cdf4c00f314ef3679 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -288,7 +288,7 @@ class Decoder(srd.Decoder):
         self.putbin(rxtx, [rxtx, bytes([b])])
         self.putbin(rxtx, [2, bytes([b])])
 
-        self.databits = [[], []]
+        self.databits[rxtx] = []
 
     def get_parity_bit(self, rxtx, signal):
         # If no parity is used/configured, skip to the next state immediately.