Add a dump from a Modbus IO module

diff --git a/uart/modbus_rtu/brainchild_io_16do/README b/uart/modbus_rtu/brainchild_io_16do/README
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+-------------------------------------------------------------------------------
+Brainchild IO-16DO Modbus communication
+-------------------------------------------------------------------------------
+
+This is a dump of Modbus data from a Brainchild IO-16DO module.
+
+It was connected to a PC using a Prolific USB-RS232 converter and a cheap
+Chinese RS232-RS485 converter.
+
+Details:
+http://www.brainchild.com.tw/en/2_1752_41579/product/16_digital_outputs_id147280.html
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Saleae Logic16 clone (at 1MHz).
+
+It was connected on the RS232 line.
+The probes were connected through 10K resistors.
+
+  Probe       UART
+  ----------------
+  0           RX
+  1           TX 
+
+
+Data
+----
+
+The sigrok command line used was:
+
+  sigrok-cli -C 0,1 -c "samplerate=1 MHz" -d saleae-logic16 -o \
+             brainchild-io-16do.sr --time 300ms
+
+The requests were sent with the included brainchild-io-16do-activity.py script.
+

diff --git a/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do-activity.py b/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do-activity.py
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+++ b/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do-activity.py
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+import time
+
+import minimalmodbus
+
+minimalmodbus.PARITY= 'E'
+
+connection = minimalmodbus.Instrument("/dev/ttyUSB0", 1)
+
+while True:
+    try:
+        time.sleep(.05)
+
+        # function 1
+        a = connection.read_bit(3, functioncode=1)
+
+        # function 2
+        b = connection.read_bit(0, functioncode=2)
+
+        # function 3
+        connection.read_register(99, functioncode=3)
+
+        # function 4
+        connection.read_register(120, functioncode=4)
+
+        # funciton 5
+        connection.write_bit(3, True, functioncode=5)
+
+        # function 6
+        connection.write_register(1, 0b01010101, functioncode=6)
+
+        # function 15
+        connection.write_bit(2, True, functioncode=15)
+
+        # function 16
+        connection.write_register(1, 0b10101010, functioncode=16)
+
+    except IOError:
+        pass

diff --git a/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do.sr b/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do.sr
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Binary files /dev/null and b/uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do.sr differ