]> sigrok.org Git - sigrok-dumps.git/commitdiff
uart: Add a Maxim MAX3232E dump (inverted signals).
authorUwe Hermann <redacted>
Thu, 11 Dec 2014 22:05:34 +0000 (23:05 +0100)
committerUwe Hermann <redacted>
Sun, 28 Dec 2014 15:05:25 +0000 (16:05 +0100)
uart/maxim_max3232e/README [new file with mode: 0644]
uart/maxim_max3232e/max3232e_hello_world_57600_8n1.sr [new file with mode: 0644]

diff --git a/uart/maxim_max3232e/README b/uart/maxim_max3232e/README
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+-------------------------------------------------------------------------------
+Maxim MAX3232E
+-------------------------------------------------------------------------------
+
+This is a set of example captures of the serial (UART) data going over
+a Maxim MAX3232E RS232 transceiver.
+
+The communication happens at 57600 baud, 8n1.
+
+Details:
+http://www.maximintegrated.com/en/products/interface/transceivers/MAX3232E.html
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was an IKALOGIC ScanaPLUS (at 100MHz):
+
+  Probe       UART
+  ----------------
+  2 (red)     MAX3232E DOUT1
+  3 (orange)  MAX3232E DIN1
+
+
+Data
+----
+
+The text "Hello world\r\n" is transmitted multiple times (DIN1 and DOUT1
+logic levels are inverted, but they both have the same data).
+
diff --git a/uart/maxim_max3232e/max3232e_hello_world_57600_8n1.sr b/uart/maxim_max3232e/max3232e_hello_world_57600_8n1.sr
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