def reset(self):
self.state = 'IDLE'
self.last_write = 0xFF # Chip port default state is high.
-
- self.logic_es = 1
- self.logic_data = []
- for i in range(NUM_OUTPUT_CHANNELS):
- self.logic_data.append(bytes([1]))
+ self.last_write_es = 0
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
self.out_logic = self.register(srd.OUTPUT_LOGIC)
+# def flush(self):
+# self.put_logic_states()
+
def putx(self, data):
self.put(self.ss, self.es, self.out_ann, data)
def put_logic_states(self):
- if (self.es > self.logic_es):
- for i in range(NUM_OUTPUT_CHANNELS):
- self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
- self.logic_es = self.es
+ if (self.es > self.last_write_es):
+ data = bytes([self.last_write])
+ self.put(self.last_write_es, self.es, self.out_logic, [0, data])
+ self.last_write_es = self.es
def handle_io(self, b):
if self.state == 'READ DATA':
'(%02X) are different' % self.last_write]])
else:
operation = ['Outputs set', 'W']
+# self.put_logic_states()
self.last_write = b
+
self.putx([1, [operation[0] + ': %02X' % b,
operation[1] + ': %02X' % b]])
- for i in range(NUM_OUTPUT_CHANNELS):
- bit = (b & (1 << i)) != 0
- self.logic_data[i] = bytes([bit])
-
def check_correct_chip(self, addr):
if addr != 0x25:
self.putx([2, ['Warning: I²C slave 0x%02X not a PCA9571 '
self.state = 'IDLE'
self.chip = -1
- self.logic_es = 1
- self.logic_data = []
- for i in range(NUM_OUTPUT_CHANNELS):
- self.logic_data.append(bytes([1]))
+ self.logic_output_es = 0
+ self.logic_value = 0
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
self.put(self.ss, self.es, self.out_ann, data)
def put_logic_states(self):
- if (self.es > self.logic_es):
- for i in range(NUM_OUTPUT_CHANNELS):
- self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
- self.logic_es = self.es
+ if (self.es > self.logic_output_es):
+ data = bytes([self.logic_value])
+ self.put(self.logic_output_es, self.es, self.out_logic, [0, data])
+ self.logic_output_es = self.es
def handle_reg_0x00(self, b):
self.putx([1, ['State of inputs: %02X' % b]])
def handle_reg_0x01(self, b):
self.putx([1, ['Outputs set: %02X' % b]])
- for i in range(NUM_OUTPUT_CHANNELS):
- bit = (b & (1 << i)) != 0
- self.logic_data[i] = bytes([bit])
+ self.logic_value = b
def handle_reg_0x02(self, b):
self.putx([1, ['Polarity inverted: %02X' % b]])
const unsigned char *data;
};
struct srd_proto_data_logic {
- int logic_class;
- uint64_t size;
- const unsigned char *data;
+ int logic_group;
+ uint64_t repeat_count; /* Number of times the value in data was repeated. */
+ const unsigned char *data; /* Bitfield containing the states of the logic outputs */
};
typedef void (*srd_pd_output_callback)(struct srd_proto_data *pdata,
struct srd_proto_data_logic *pdl;
PyObject *py_tmp;
Py_ssize_t size;
- int logic_class;
- char *class_name, *buf;
+ int logic_group;
+ char *group_name, *buf;
PyGILState_STATE gstate;
gstate = PyGILState_Ensure();
- /* Should be a list of [logic class, bytes]. */
+ /* Should be a list of [logic group, bytes]. */
if (!PyList_Check(obj)) {
srd_err("Protocol decoder %s submitted non-list for SRD_OUTPUT_LOGIC.",
di->decoder->name);
"but first element was not an integer.", di->decoder->name);
goto err;
}
- logic_class = PyLong_AsLong(py_tmp);
- if (!(class_name = g_slist_nth_data(di->decoder->logic_output_channels, logic_class))) {
+ logic_group = PyLong_AsLong(py_tmp);
+ if (!(group_name = g_slist_nth_data(di->decoder->logic_output_channels, logic_group))) {
srd_err("Protocol decoder %s submitted SRD_OUTPUT_LOGIC with "
- "unregistered logic class %d.", di->decoder->name, logic_class);
+ "unregistered logic group %d.", di->decoder->name, logic_group);
goto err;
}
PyGILState_Release(gstate);
pdl = pdata->data;
- pdl->logic_class = logic_class;
- pdl->size = size;
- if (!(pdl->data = g_try_malloc(pdl->size)))
+ pdl->logic_group = logic_group;
+ /* pdl->repeat_count is set by the caller as it depends on the sample range */
+ if (!(pdl->data = g_try_malloc(size)))
return SRD_ERR_MALLOC;
- memcpy((void *)pdl->data, (const void *)buf, pdl->size);
+ memcpy((void *)pdl->data, (const void *)buf, size);
return SRD_OK;
struct srd_proto_data pdata;
struct srd_proto_data_annotation pda;
struct srd_proto_data_binary pdb;
+ struct srd_proto_data_logic pdl;
uint64_t start_sample, end_sample;
int output_id;
struct srd_pd_callback *cb;
break;
case SRD_OUTPUT_LOGIC:
if ((cb = srd_pd_output_callback_find(di->sess, pdo->output_type))) {
- pdata.data = &pdb;
+ pdata.data = &pdl;
/* Convert from PyDict to srd_proto_data_logic. */
if (convert_logic(di, py_data, &pdata) != SRD_OK) {
/* An error was already logged. */
break;
}
+ if (end_sample <= start_sample) {
+ srd_err("Ignored SRD_OUTPUT_LOGIC with invalid sample range.");
+ break;
+ }
+ pdl.repeat_count = (end_sample - start_sample) - 1;
Py_BEGIN_ALLOW_THREADS
cb->cb(&pdata, cb->cb_data);
Py_END_ALLOW_THREADS