static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
const char *bitstream_fname)
{
- struct dev_context *devc;
struct drv_context *drvc;
struct sr_usb_dev_inst *usb;
struct sr_resource bitstream;
+ uint32_t bitstream_size;
uint8_t buffer[sizeof(uint32_t)];
uint8_t *wrptr;
uint8_t block[4096];
int len, act_len;
unsigned int pos;
int ret;
- unsigned int zero_pad_to = 0x2c000;
+ unsigned int zero_pad_to;
- devc = sdi->priv;
drvc = sdi->driver->context;
usb = sdi->conn;
return ret;
}
- devc->bitstream_size = (uint32_t)bitstream.size;
+ bitstream_size = (uint32_t)bitstream.size;
wrptr = buffer;
- write_u32le_inc(&wrptr, devc->bitstream_size);
+ write_u32le_inc(&wrptr, bitstream_size);
if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
sr_err("Cannot initiate FPGA bitstream upload.");
sr_resource_close(drvc->sr_ctx, &bitstream);
return ret;
}
+ zero_pad_to = bitstream_size;
+ zero_pad_to += LA2016_EP2_PADDING - 1;
+ zero_pad_to /= LA2016_EP2_PADDING;
+ zero_pad_to *= LA2016_EP2_PADDING;
pos = 0;
while (1) {
#define RENUM_GONE_DELAY_MS 1800
#define RENUM_POLL_INTERVAL_MS 200
+/*
+ * The device expects some zero padding to follow the content of the
+ * file which contains the FPGA bitstream. Specify the chunk size here.
+ */
+#define LA2016_EP2_PADDING 2048
+
#define LA2016_THR_VOLTAGE_MIN 0.40
#define LA2016_THR_VOLTAGE_MAX 4.00
uint16_t cur_channels;
int num_channels;
- uint32_t bitstream_size;
-
/* Values derived from user specs. */
uint64_t pre_trigger_size;