* 6 1 = samplerate 400MHz
* 5 1 = samplerate 200MHz or analog mode
* 4 0 = logic, 1 = dso or analog
- * 3 unused
+ * 3 1 = RLE encoding (enable for more than 16 Megasamples)
* 1-2 00 = internal clock,
* 01 = external clock rising,
* 11 = external clock falling
v16 |= 1 << 2;
}
}
+ if (devc->limit_samples > DS_MAX_LOGIC_DEPTH && !devc->dslogic_continuous_mode){
+ /* enable rle for long captures.
+ Without this, captured data present errors. */
+ v16 |= 1<< 3;
+ }
WL16(&cfg.mode, v16);
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
#define DS_START_FLAGS_MODE_LA (1 << 4)
+/* enable rle to capture more samples than this limit */
+#define DS_MAX_LOGIC_DEPTH 16000000
+
enum dslogic_operation_modes {
DS_OP_NORMAL,
DS_OP_INTERNAL_TEST,