link-mso19: Added new register definitions and renamed variables to reflect new findings.

diff --git a/hardware/link-mso19/link-mso19.c b/hardware/link-mso19/link-mso19.c
index 8b06151a3cbbca2a63943559689743e979081691..ccc4d9907d37dd295c1b0a5c8bad121532bdb88e 100644 (file)
--- a/hardware/link-mso19/link-mso19.c
+++ b/hardware/link-mso19/link-mso19.c
@@ -142,9 +142,9 @@ static int mso_reset_adc(struct sr_device_instance *sdi)
        struct mso *mso = sdi->priv;
        uint16_t ops[2];
 
-       ops[0] = mso_trans(REG_CTL, (mso->ctlbase | BIT_CTL_RESETADC));
-       ops[1] = mso_trans(REG_CTL, mso->ctlbase);
-       mso->ctlbase |= BIT_CTL_ADC_UNKNOWN4;
+       ops[0] = mso_trans(REG_CTL1, (mso->ctlbase1 | BIT_CTL1_RESETADC));
+       ops[1] = mso_trans(REG_CTL1, mso->ctlbase1);
+       mso->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
 }
@@ -154,8 +154,8 @@ static int mso_reset_fsm(struct sr_device_instance *sdi)
        struct mso *mso = sdi->priv;
        uint16_t ops[1];
 
-       mso->ctlbase |= BIT_CTL_RESETFSM;
-       ops[0] = mso_trans(REG_CTL, mso->ctlbase);
+       mso->ctlbase1 |= BIT_CTL1_RESETFSM;
+       ops[0] = mso_trans(REG_CTL1, mso->ctlbase1);
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
 }
@@ -165,10 +165,10 @@ static int mso_toggle_led(struct sr_device_instance *sdi, int state)
        struct mso *mso = sdi->priv;
        uint16_t ops[1];
 
-       mso->ctlbase &= BIT_CTL_LED;
+       mso->ctlbase1 &= BIT_CTL1_LED;
        if (state)
-               mso->ctlbase |= BIT_CTL_LED;
-       ops[0] = mso_trans(REG_CTL, mso->ctlbase);
+               mso->ctlbase1 |= BIT_CTL1_LED;
+       ops[0] = mso_trans(REG_CTL1, mso->ctlbase1);
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
 }
@@ -203,9 +203,9 @@ static int mso_arm(struct sr_device_instance *sdi)
 {
        struct mso *mso = sdi->priv;
        uint16_t ops[] = {
-               mso_trans(REG_CTL, mso->ctlbase | BIT_CTL_RESETFSM),
-               mso_trans(REG_CTL, mso->ctlbase | BIT_CTL_ARM),
-               mso_trans(REG_CTL, mso->ctlbase),
+               mso_trans(REG_CTL1, mso->ctlbase1 | BIT_CTL1_RESETFSM),
+               mso_trans(REG_CTL1, mso->ctlbase1 | BIT_CTL1_ARM),
+               mso_trans(REG_CTL1, mso->ctlbase1),
        };
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
@@ -215,8 +215,8 @@ static int mso_force_capture(struct sr_device_instance *sdi)
 {
        struct mso *mso = sdi->priv;
        uint16_t ops[] = {
-               mso_trans(REG_CTL, mso->ctlbase | 8),
-               mso_trans(REG_CTL, mso->ctlbase),
+               mso_trans(REG_CTL1, mso->ctlbase1 | 8),
+               mso_trans(REG_CTL1, mso->ctlbase1),
        };
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
@@ -228,7 +228,7 @@ static int mso_dac_out(struct sr_device_instance *sdi, uint16_t val)
        uint16_t ops[] = {
                mso_trans(REG_DAC1, (val >> 8) & 0xff),
                mso_trans(REG_DAC2, val & 0xff),
-               mso_trans(REG_CTL, mso->ctlbase | BIT_CTL_RESETADC),
+               mso_trans(REG_CTL1, mso->ctlbase1 | BIT_CTL1_RESETADC),
        };
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
@@ -253,7 +253,7 @@ static int mso_configure_rate(struct sr_device_instance *sdi,
 
        for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
                if (rate_map[i].rate == rate) {
-                       mso->slowmode = rate_map[i].slowmode;
+                       mso->ctlbase2 = rate_map[i].slowmode;
                        ret = mso_clkrate_out(sdi, rate_map[i].val);
                        if (ret == SR_OK)
                                mso->cur_rate = rate;
@@ -323,7 +323,7 @@ static int mso_configure_trigger(struct sr_device_instance *sdi)
        ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
        ops[4] = mso_trans(11,
                        mso->dso_trigger_width / SR_HZ_TO_NS(mso->cur_rate));
-       ops[5] = mso_trans(15, (2 | mso->slowmode));
+       ops[5] = mso_trans(REG_CTL2, (mso->ctlbase2 | BITS_CTL2_BANK(2)));
 
        /* FIXME SPI/I2C Triggers */
        ops[6] = mso_trans(0, 0);
@@ -335,7 +335,7 @@ static int mso_configure_trigger(struct sr_device_instance *sdi)
        ops[12] = mso_trans(6, 0xff);
        ops[13] = mso_trans(7, 0xff);
        ops[14] = mso_trans(8, mso->trigger_spimode);
-       ops[15] = mso_trans(15, mso->slowmode);
+       ops[15] = mso_trans(REG_CTL2, mso->ctlbase2);
 
        return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
 }
@@ -461,7 +461,7 @@ static int hw_init(const char *deviceinfo)
                }
                sprintf(hwrev, "r%d", mso->hwrev);
                /* hardware initial state */
-               mso->ctlbase = 0;
+               mso->ctlbase1 = 0;
 
                sdi = sr_device_instance_new(devcnt, SR_ST_INITIALIZING,
                        manufacturer, product, hwrev);
@@ -731,8 +731,8 @@ static int hw_start_acquisition(int device_index, gpointer session_device_id)
 //             return ret;
 
        /* FIXME: ACDC Mode */
-       mso->ctlbase &= 0x7f;
-//     mso->ctlbase |= mso->acdcmode;
+       mso->ctlbase1 &= 0x7f;
+//     mso->ctlbase1 |= mso->acdcmode;
 
        ret = mso_configure_rate(sdi, mso->cur_rate);
        if (ret != SR_OK)

diff --git a/hardware/link-mso19/link-mso19.h b/hardware/link-mso19/link-mso19.h
index f88ee723c536976948330ad19c3187ccc5c1d834..506b34697e159891d1627777072ead38d4143988 100644 (file)
--- a/hardware/link-mso19/link-mso19.h
+++ b/hardware/link-mso19/link-mso19.h
@@ -63,8 +63,8 @@ struct mso {
        uint16_t dac_offset;
        uint16_t offset_range;
        /* register cache */
-       uint8_t ctlbase;
-       uint8_t slowmode;
+       uint8_t ctlbase1;
+       uint8_t ctlbase2;
        /* state */
        uint8_t la_threshold;
        uint64_t cur_rate;
@@ -91,21 +91,34 @@ struct mso {
 const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
 const char mso_foot[] = { 0x7e };
 
-/* registers */
+/* bank agnostic registers */
+#define REG_CTL2               15
+
+/* bank 0 registers */
 #define REG_BUFFER             1
 #define REG_TRIGGER            2
 #define REG_CLKRATE1           9
 #define REG_CLKRATE2           10
 #define REG_DAC1               12
 #define REG_DAC2               13
-#define REG_CTL                        14
+/* possibly bank agnostic: */
+#define REG_CTL1               14
+
+/* bank 2 registers (SPI/I2C protocol trigger) */
+#define REG_PT_WORD(x)        (x)
+#define REG_PT_MASK(x)        (x+4)
+#define REG_PT_SPIMODE          8
+
+/* bits - REG_CTL1 */
+#define BIT_CTL1_RESETFSM      (1 << 0)
+#define BIT_CTL1_ARM          (1 << 1)
+#define BIT_CTL1_ADC_UNKNOWN4  (1 << 4) /* adc enable? */
+#define BIT_CTL1_RESETADC      (1 << 6)
+#define BIT_CTL1_LED          (1 << 7)
 
-/* bits */
-#define BIT_CTL_RESETFSM       (1 << 0)
-#define BIT_CTL_ARM            (1 << 1)
-#define BIT_CTL_ADC_UNKNOWN4   (1 << 4) /* adc enable? */
-#define BIT_CTL_RESETADC       (1 << 6)
-#define BIT_CTL_LED            (1 << 7)
+/* bits - REG_CTL2 */
+#define BITS_CTL2_BANK(x)      (x & 0x3)
+#define BIT_CTL2_SLOWMODE      (1 << 5)
 
 struct rate_map {
        uint32_t rate;