}
/* Enter trigger programming mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
+ sigma_set_register(WRITE_TRIGGER_SELECT2, 0x20, devc);
triggerselect = 0;
if (devc->cur_samplerate >= SR_MHZ(100)) {
/* 100 and 200 MHz mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
+ sigma_set_register(WRITE_TRIGGER_SELECT2, 0x81, devc);
/* Find which pin to trigger on from mask. */
for (triggerpin = 0; triggerpin < 8; triggerpin++)
sizeof(struct triggerinout), devc);
/* Go back to normal mode. */
- sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
+ sigma_set_register(WRITE_TRIGGER_SELECT2, triggerselect, devc);
/* Set clock select register. */
clockselect.async = 0;
if (lut->m1d[3] & bit)
tmp[1] |= 0x80;
- sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
+ sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp),
devc);
- sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
+ sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc);
}
/* Send the parameters */
- sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
+ sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params,
sizeof(lut->params), devc);
return SR_OK;
enum sigma_write_register {
WRITE_CLOCK_SELECT = 0,
- WRITE_TRIGGER_SELECT0 = 1,
- WRITE_TRIGGER_SELECT1 = 2,
+ WRITE_TRIGGER_SELECT = 1,
+ WRITE_TRIGGER_SELECT2 = 2,
WRITE_MODE = 3,
WRITE_MEMROW = 4,
WRITE_POST_TRIGGER = 5,
WRITE_TRIGGER_OPTION = 6,
WRITE_PIN_VIEW = 7,
-
+ /* Unassigned register locations. */
WRITE_TEST = 15,
};
READ_PIN_CHANGE_HIGH = 9,
READ_BLOCK_LAST_TS_LOW = 10,
READ_BLOCK_LAST_TS_HIGH = 11,
- READ_PIN_VIEW = 12,
-
+ READ_BLOCK_TS_OVERRUN = 12,
+ READ_PIN_VIEW = 13,
+ /* Unassigned register location. */
READ_TEST = 15,
};