('error', 'Error'),
)
annotation_rows = (
- ('name', 'Logical', (1, 2, 5, 6, 7, 8)),
- ('data', 'Data', (9,)),
('bits', 'Bits', (0, 3, 4)),
+ ('data', 'Data', (9,)),
+ ('name', 'Logical', (1, 2, 5, 6, 7, 8)),
('errors', 'Errors', (10,)),
)
('sections', 'EDID structure sections'),
)
annotation_rows = (
- ('sections', 'Sections', (1,)),
('fields', 'Fields', (0,)),
+ ('sections', 'Sections', (1,)),
)
def __init__(self):
('warning', 'Warning'),
)
annotation_rows = (
+ ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
('commands', 'Commands',
(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
- ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
('warnings', 'Warnings', (ANN_WARNING,)),
)
)
annotation_rows = (
('instructions', 'Instructions', (0,)),
- ('regs', 'Registers', regs_items['rows_range']),
('control_fields_in', 'Control fields in', (10,)),
('control_fields_out', 'Control fields out', (11,)),
+ ('regs', 'Registers', regs_items['rows_range']),
('pracc', 'PrAcc', (12,)),
)
)
annotation_rows = (
('bits', 'Bits', (ann_cmdbit, ann_databit)),
- ('commands', 'Commands', (ann_cmd,)),
('data', 'Data', (ann_data,)),
+ ('commands', 'Commands', (ann_cmd,)),
('warnings', 'Warnings', (ann_warning,)),
)
('parity', 'Parity Bit'),
)
annotation_rows = (
- ('info', 'Info', (0, 1, 3, 5, 6, 7, 8)),
('bits', 'Bits', (2,)),
+ ('info', 'Info', (0, 1, 3, 5, 6, 7, 8)),
('samples', 'Samples', (4,)),
)
('tx-packet', 'TX packet'),
)
annotation_rows = (
- ('rx-data', 'RX', (0, 2, 4, 6, 8)),
('rx-data-bits', 'RX bits', (12,)),
+ ('rx-data', 'RX', (0, 2, 4, 6, 8)),
('rx-warnings', 'RX warnings', (10,)),
('rx-break', 'RX break', (14,)),
('rx-packets', 'RX packets', (16,)),
- ('tx-data', 'TX', (1, 3, 5, 7, 9)),
('tx-data-bits', 'TX bits', (13,)),
+ ('tx-data', 'TX', (1, 3, 5, 7, 9)),
('tx-warnings', 'TX warnings', (11,)),
('tx-break', 'TX break', (15,)),
('tx-packets', 'TX packets', (17,)),