Until now the I2C PD was basically ignoring the very first sample, and
using that as the initial 'oldscl'/'oldsda' value.
However, if your logic analyzers trigger on, say, SDA=low that will
result in a file where the first sample is really important since it
is the one which the PD will need to know that there's a falling edge
on SDA.
Thus, assume both SCL and SDA are high/1 when the PD starts. This is
a good assumption since both pins have pullups on them in practice
and are thus high/1 when the bus is idle.
Later on we might want to have config options to let the PD assume
other states of SDA/SCL initially.
self.wr = -1
self.is_repeat_start = 0
self.state = 'FIND START'
- self.oldscl = None
- self.oldsda = None
- self.oldpins = None
+ self.oldscl = 1
+ self.oldsda = 1
+ self.oldpins = (1, 1)
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
continue
self.oldpins, (scl, sda) = pins, pins
- # First sample: Save SCL/SDA value.
- if self.oldscl == None:
- self.oldscl = scl
- self.oldsda = sda
- continue
-
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.