dslogic: Added half and quater-mode flags

diff --git a/src/hardware/dslogic/dslogic.c b/src/hardware/dslogic/dslogic.c
index 4d466143f822495adf8d934473f16e81416b8f0a..297af2b0ae6bc0d5f40b8c3f7ffb26efcc1e3a18 100644 (file)
--- a/src/hardware/dslogic/dslogic.c
+++ b/src/hardware/dslogic/dslogic.c
@@ -345,6 +345,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                v16 = DS_MODE_EXT_TEST;
        else if (devc->mode == DS_OP_LOOPBACK_TEST)
                v16 = DS_MODE_LPB_TEST;
+
+       if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
+               v16 |= DS_MODE_HALF_MODE;
+       else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
+               v16 |= DS_MODE_QUAR_MODE;
+
        if (devc->continuous_mode)
                v16 |= DS_MODE_STREAM_MODE;
        if (devc->external_clock) {