]> sigrok.org Git - libsigrok.git/commitdiff
saleae-logic16: Clearer error message.
authorBert Vermeulen <redacted>
Thu, 27 Nov 2014 00:00:40 +0000 (01:00 +0100)
committerBert Vermeulen <redacted>
Thu, 27 Nov 2014 00:01:13 +0000 (01:01 +0100)
src/hardware/saleae-logic16/protocol.c

index bd96e634e57b20c14c254ce5f619b6e67ffef5b9..d60bf3e7a50aa20c4236b072aaf864a743adc698 100644 (file)
@@ -470,7 +470,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
        reg1 &= ~0x20;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
+               sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08.", reg1);
                return SR_ERR;
        }
 
@@ -499,7 +499,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
                return ret;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. "
+               sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
                       "Proceeding anyway.", reg1);
        }
 
@@ -507,7 +507,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
                return ret;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.",
+               sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x.",
                       reg10, clock_select);
                return SR_ERR;
        }