The Saleae Logic exported files (Logic2 digital format) don't contain a
samplerate, so users need to specify the value. For values smaller than
the samplerate that was used during the capture undersampling will take
place. An implementation detail of the input module could result in
incorrect timing of sample values in the session feed. In extreme cases
none of the periods between signal edges qualified for submission. In
that case no sample data was sent to the sigrok session at all.
$ sigrok-cli -i digital_1.bin -I saleae:samplerate=1000
Keep the very timestamp at hand when the last sample data was submitted.
Only advance that timestamp when more sample data was sent. This avoids
the accumulation of timing errors for undersampling scenarios, and does
forward undersampled input data when the user provided sample period has
passed.
This fixes bug #1600.
diff_time /= inc->logic_state.l2d.sample_period;
diff_time += 0.5;
count = (uint64_t)diff_time;
- digital = inc->feed.last.digital;
- rc = addto_feed_buffer_logic(in, digital, count);
- if (rc)
- return rc;
- inc->feed.last.time = next_time;
+ if (count) {
+ digital = inc->feed.last.digital;
+ rc = addto_feed_buffer_logic(in, digital, count);
+ if (rc)
+ return rc;
+ inc->feed.last.time = next_time;
+ }
inc->feed.last.digital = 1 - inc->feed.last.digital;
return SR_OK;
case STAGE_L2A_FIRST_VALUE: