uart: Use consistent order of steps when processing samples

Slightly rearrange some of the methods which are involved in UART frame
inspection. Use a consistent sequence of steps: Grab the signal's
current value, accumulate and process the information, emit respective
annotations, and advance to the next stage in the UART frame inspection.

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 6a0dff9dfc8f36bc7d893c5e441ea5d4e57bd880..152b8538e0f187e362e2317972b2d23ccf46bcc8 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -216,11 +216,11 @@ class Decoder(srd.Decoder):
         self.datavalue[rxtx] = 0
         self.startsample[rxtx] = -1
 
-        self.state[rxtx] = 'GET DATA BITS'
-
         self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
         self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
 
+        self.state[rxtx] = 'GET DATA BITS'
+
     def get_data_bits(self, rxtx, signal):
         # Save the sample number of the middle of the first data bit.
         if self.startsample[rxtx] == -1:
@@ -246,12 +246,6 @@ class Decoder(srd.Decoder):
         if self.cur_data_bit[rxtx] < self.options['num_data_bits']:
             return
 
-        # Skip to either reception of the parity bit, or reception of
-        # the STOP bits if parity is not applicable.
-        self.state[rxtx] = 'GET PARITY BIT'
-        if self.options['parity_type'] == 'none':
-            self.state[rxtx] = 'GET STOP BITS'
-
         self.putpx(rxtx, ['DATA', rxtx,
             (self.datavalue[rxtx], self.databits[rxtx])])
 
@@ -266,6 +260,12 @@ class Decoder(srd.Decoder):
 
         self.databits[rxtx] = []
 
+        # Advance to either reception of the parity bit, or reception of
+        # the STOP bits if parity is not applicable.
+        self.state[rxtx] = 'GET PARITY BIT'
+        if self.options['parity_type'] == 'none':
+            self.state[rxtx] = 'GET STOP BITS'
+
     def format_value(self, v):
         # Format value 'v' according to configured options.
         # Reflects the user selected kind of representation, as well as
@@ -311,8 +311,6 @@ class Decoder(srd.Decoder):
     def get_parity_bit(self, rxtx, signal):
         self.paritybit[rxtx] = signal
 
-        self.state[rxtx] = 'GET STOP BITS'
-
         if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
                      self.datavalue[rxtx], self.options['num_data_bits']):
             self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
@@ -322,6 +320,8 @@ class Decoder(srd.Decoder):
             self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
             self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
 
+        self.state[rxtx] = 'GET STOP BITS'
+
     # TODO: Currently only supports 1 stop bit.
     def get_stop_bits(self, rxtx, signal):
         self.stopbit1[rxtx] = signal
@@ -332,11 +332,11 @@ class Decoder(srd.Decoder):
             self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
             # TODO: Abort? Ignore the frame? Other?
 
-        self.state[rxtx] = 'WAIT FOR START BIT'
-
         self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
         self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
 
+        self.state[rxtx] = 'WAIT FOR START BIT'
+
     def get_wait_cond(self, rxtx, inv):
         """
         Determine Decoder.wait() condition for specified UART line.