def __init__(self, **kwargs):
self.state = 'IDLE'
self.mosi_bytes, self.miso_bytes = [], []
- self.cmd_ss, self.cmd_es = 0, 0
+ self.ss_cmd, self.es_cmd = 0, 0
self.xx, self.yy, self.zz, self.mm = 0, 0, 0, 0
- self.device_ss = None
+ self.ss_device = None
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
def putx(self, data):
- self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
+ self.put(self.ss_cmd, self.es_cmd, self.out_ann, data)
def handle_cmd_programming_enable(self, cmd, ret):
# Programming enable.
# Store for later.
self.mm = cmd[3]
- self.device_ss = self.cmd_ss
+ self.ss_device = self.ss_cmd
# Sanity check on reply.
if ret[1] != 0x30 or ret[2] != cmd[1] or ret[0] != self.yy:
p = part[(self.part_fam_flash_size, self.part_number)]
data = [9, ['Device: Atmel %s' % p]]
- self.put(self.device_ss, self.cmd_es, self.out_ann, data)
+ self.put(self.ss_device, self.es_cmd, self.out_ann, data)
# Sanity check on reply.
if ret[1] != 0x30 or ret[2] != self.xx or ret[0] != self.mm:
self.ss, self.es = ss, es
if len(self.mosi_bytes) == 0:
- self.cmd_ss = ss
+ self.ss_cmd = ss
# Append new bytes.
self.mosi_bytes.append(mosi)
if len(self.mosi_bytes) < 4:
return
- self.cmd_es = es
+ self.es_cmd = es
self.handle_command(self.mosi_bytes, self.miso_bytes)
d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
days_of_week[self.days - 1], self.date, self.months,
self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, self.es, self.out_ann,
+ self.put(self.ss_block, self.es, self.out_ann,
[cls, ['%s date/time: %s' % (rw, d)]])
def handle_reg(self, b):
def is_correct_chip(self, addr):
if addr == DS1307_I2C_ADDRESS:
return True
- self.put(self.block_start_sample, self.es, self.out_ann,
+ self.put(self.ss_block, self.es, self.out_ann,
[28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
return False
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
+ self.ss_block = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
if cmd != 'ADDRESS WRITE':
def __init__(self, **kwargs):
self.samplerate = None
- self.ss = self.es = self.byte_ss = -1
+ self.ss = self.es = self.ss_byte = -1
self.samplenum = None
self.bitcount = 0
self.databyte = 0
# Remember the start of the first data/address bit.
if self.bitcount == 0:
- self.byte_ss = self.samplenum
+ self.ss_byte = self.samplenum
# Store individual bits and their start/end samplenumbers.
# In the list, index 0 represents the LSB (I²C transmits MSB-first).
cmd = 'DATA READ'
bin_class = 2
- self.ss, self.es = self.byte_ss, self.samplenum + self.bitwidth
+ self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth
self.putp(['BITS', self.bits])
self.putp([cmd, d])
self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R']
self.putx([proto[cmd][0], w])
- self.ss, self.es = self.byte_ss, self.samplenum
+ self.ss, self.es = self.ss_byte, self.samplenum
self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
'%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
# Meta bitrate
elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
bitrate = int(1 / elapsed * self.pdu_bits)
- self.put(self.byte_ss, self.samplenum, self.out_bitrate, bitrate)
+ self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate)
cmd = 'STOP'
self.ss, self.es = self.samplenum, self.samplenum
self.data = 0
self.samplesreceived = 0
self.first_sample = None
- self.start_sample = None
+ self.ss_block = None
self.wordlength = -1
self.wrote_wav_header = False
self.samplerate = value
def putpb(self, data):
- self.put(self.start_sample, self.samplenum, self.out_python, data)
+ self.put(self.ss_block, self.samplenum, self.out_python, data)
def putbin(self, data):
- self.put(self.start_sample, self.samplenum, self.out_bin, data)
+ self.put(self.ss_block, self.samplenum, self.out_bin, data)
def putb(self, data):
- self.put(self.start_sample, self.samplenum, self.out_ann, data)
+ self.put(self.ss_block, self.samplenum, self.out_ann, data)
def report(self):
# Calculate the sample rate.
samplerate = '?'
- if self.start_sample is not None and \
+ if self.ss_block is not None and \
self.first_sample is not None and \
- self.start_sample > self.first_sample:
+ self.ss_block > self.first_sample:
samplerate = '%d' % (self.samplesreceived *
- self.samplerate / (self.start_sample -
+ self.samplerate / (self.ss_block -
self.first_sample))
return 'I²S: %d %d-bit samples received at %sHz' % \
continue
# Only submit the sample, if we received the beginning of it.
- if self.start_sample is not None:
+ if self.ss_block is not None:
if not self.wrote_wav_header:
self.put(0, 0, self.out_bin, (0, self.wav_header()))
# Reset decoder state.
self.data = 0
self.bitcount = 0
- self.start_sample = self.samplenum
+ self.ss_block = self.samplenum
# Save the first sample position.
if self.first_sample is None:
def __init__(self, **kwargs):
self.samplerate = None
self.samplenum = None
- self.edges, self.bits, self.bits_ss_es = [], [], []
+ self.edges, self.bits, self.ss_es_bits = [], [], []
self.state = 'IDLE'
def start(self):
self.halfbit = int((self.samplerate * 0.00178) / 2.0)
def putb(self, bit1, bit2, data):
- ss, es = self.bits_ss_es[bit1][0], self.bits_ss_es[bit2][1]
+ ss, es = self.ss_es_bits[bit1][0], self.ss_es_bits[bit2][1]
self.put(ss, es, self.out_ann, data)
def handle_bits(self):
if i == 0:
ss = max(0, self.bits[0][0] - self.halfbit)
else:
- ss = self.bits_ss_es[i - 1][1]
+ ss = self.ss_es_bits[i - 1][1]
es = self.bits[i][0] + self.halfbit
- self.bits_ss_es.append([ss, es])
+ self.ss_es_bits.append([ss, es])
self.putb(i, i, [0, ['%d' % self.bits[i][1]]])
# Bits[0:0]: Startbit 1
s = ['Startbit1: %d' % b[0][1], 'SB1: %d' % b[0][1], 'SB1', 'S1', 'S']
return 'e' # Error, invalid edge distance.
def reset_decoder_state(self):
- self.edges, self.bits, self.bits_ss_es = [], [], []
+ self.edges, self.bits, self.ss_es_bits = [], [], []
self.state = 'IDLE'
def decode(self, ss, es, data):
def putb(self, data):
# Helper for annotations which span a block of I²C packets.
- self.put(self.block_start, self.block_end, self.out_ann, data)
+ self.put(self.ss_block, self.es_block, self.out_ann, data)
def warn_upon_invalid_slave(self, addr):
# LM75 and compatible devices have a 7-bit I²C slave address where
def handle_temperature_reg(self, b, s, rw):
# Common helper for the temperature/T_HYST/T_OS registers.
if len(self.databytes) == 0:
- self.block_start = self.ss
+ self.ss_block = self.ss
self.databytes.append(b)
return
self.databytes.append(b)
- self.block_end = self.es
+ self.es_block = self.es
self.output_temperature(s, rw)
self.databytes = []
def handle_rdid(self, mosi, miso):
if self.cmdstate == 1:
# Byte 1: Master sends command ID.
- self.start_sample = self.ss
+ self.ss_block = self.ss
self.putx([2, ['Command: %s' % cmds[self.state][1]]])
elif self.cmdstate == 2:
# Byte 2: Slave sends the JEDEC manufacturer ID.
# TODO: Check self.device_id is valid & exists in device_names.
# TODO: Same device ID? Check!
d = 'Device: Macronix %s' % device_name[self.device_id]
- self.put(self.start_sample, self.es, self.out_ann, [0, [d]])
+ self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
self.state = None
else:
self.cmdstate += 1
if self.cmdstate == 1:
# Byte 1: Master sends command ID.
self.addr = 0
- self.start_sample = self.ss
+ self.ss_block = self.ss
self.putx([8, ['Command: %s' % cmds[self.state][1]]])
elif self.cmdstate in (2, 3, 4):
# Bytes 2/3/4: Master sends sectror address (24bits, MSB-first).
if self.cmdstate == 4:
d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
- self.put(self.start_sample, self.es, self.out_ann, [24, [d]])
+ self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
# TODO: Max. size depends on chip, check that too if possible.
if self.addr % 4096 != 0:
# Sector addresses must be 4K-aligned (same for all 3 chips).
d = 'Warning: Invalid sector address!'
- self.put(self.start_sample, self.es, self.out_ann, [101, [d]])
+ self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
self.state = None
else:
self.cmdstate += 1
def handle_rems(self, mosi, miso):
if self.cmdstate == 1:
# Byte 1: Master sends command ID.
- self.start_sample = self.ss
+ self.ss_block = self.ss
self.putx([16, ['Command: %s' % cmds[self.state][1]]])
elif self.cmdstate in (2, 3):
# Bytes 2/3: Master sends two dummy bytes.
self.putx([24, ['%s ID' % d]])
if self.cmdstate == 6:
- self.end_sample = self.es
id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
self.putx([24, ['Device: Macronix %s' % device_name[id]]])
self.state = None
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
# TODO: We should only handle packets to the slave(?)
self.sx = self.sy = self.ax = self.ay = self.az = self.bz = self.bc = -1
self.databytecount = 0
self.reg = 0x00
- self.ss = self.es = self.block_ss = self.block_es = 0
+ self.ss = self.es = self.ss_block = self.es_block = 0
self.init_seq = []
def start(self):
self.put(self.ss, self.es, self.out_ann, data)
def putb(self, data):
- self.put(self.block_ss, self.block_es, self.out_ann, data)
+ self.put(self.ss_block, self.es_block, self.out_ann, data)
def putd(self, bit1, bit2, data):
self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
def handle_reg_0x00(self, databyte):
- self.block_ss = self.ss
+ self.ss_block = self.ss
self.sx = databyte
self.putx([0, ['Analog stick X position: 0x%02X' % self.sx,
'SX: 0x%02X' % self.sx]])
'AZ[9:2]: 0x%03X' % self.az]])
def handle_reg_0x05(self, databyte):
- self.block_es = self.es
+ self.es_block = self.es
self.bz = (databyte & (1 << 0)) >> 0 # Bits[0:0]
self.bc = (databyte & (1 << 1)) >> 1 # Bits[1:1]
ax_rest = (databyte & (3 << 2)) >> 2 # Bits[3:2]
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
+ self.ss_block = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address read/write operation.
if cmd == 'ADDRESS READ':
handle_reg(databyte)
self.reg += 1
elif cmd == 'STOP':
- self.block_end_sample = es
+ self.es_block = es
self.output_full_block_if_possible()
self.sx = self.sy = self.ax = self.ay = self.az = -1
self.bz = self.bc = -1
if cmd == 'DATA WRITE':
self.handle_reg_write(databyte)
elif cmd == 'STOP':
- self.block_end_sample = es
+ self.es_block = es
self.output_init_seq()
self.init_seq = []
self.state = 'IDLE'
)
def __init__(self, **kwargs):
- self.beg = 0
- self.end = 0
+ self.ss_block = 0
+ self.es_block = 0
self.state = 'COMMAND'
self.bit_cnt = 0
self.search = 'P'
def putx(self, data):
# Helper function for most annotations.
- self.put(self.beg, self.end, self.out_ann, data)
+ self.put(self.ss_block, self.es_block, self.out_ann, data)
def puty(self, data):
# Helper function for most protocol packets.
- self.put(self.beg, self.end, self.out_python, data)
+ self.put(self.ss_block, self.es_block, self.out_python, data)
def decode(self, ss, es, data):
code, val = data
def onewire_collect(self, length, val, ss, es):
# Storing the sample this sequence begins with.
if self.bit_cnt == 1:
- self.beg = ss
+ self.ss_block = ss
self.data = self.data & ~(1 << self.bit_cnt) | (val << self.bit_cnt)
self.bit_cnt += 1
# Storing the sample this sequence ends with.
# In case the full length of the sequence is received, return 1.
if self.bit_cnt == length:
- self.end = es
+ self.es_block = es
self.data = self.data & ((1 << length) - 1)
self.bit_cnt = 0
return 1
def onewire_search(self, length, val, ss, es):
# Storing the sample this sequence begins with.
if (self.bit_cnt == 0) and (self.search == 'P'):
- self.beg = ss
+ self.ss_block = ss
if self.search == 'P':
# Master receives an original address bit.
# Storing the sample this sequence ends with.
# In case the full length of the sequence is received, return 1.
if self.bit_cnt == length:
- self.end = es
+ self.es_block = es
self.data_p = self.data_p & ((1 << length) - 1)
self.data_n = self.data_n & ((1 << length) - 1)
self.data = self.data & ((1 << length) - 1)
)
def __init__(self, **kwargs):
- self.cmd_ss, self.cmd_es = 0, 0
+ self.ss_cmd, self.es_cmd = 0, 0
self.mosi_bytes = []
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
def putx(self, data):
- self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
+ self.put(self.ss_cmd, self.es_cmd, self.out_ann, data)
def decode(self, ss, es, data):
ptype, mosi, miso = data
self.ss, self.es = ss, es
if len(self.mosi_bytes) == 0:
- self.cmd_ss = ss
+ self.ss_cmd = ss
self.mosi_bytes.append(mosi)
# RGB value == 3 bytes
red, green, blue = self.mosi_bytes
rgb_value = int(red) << 16 | int(green) << 8 | int(blue)
- self.cmd_es = es
+ self.es_cmd = es
self.putx([0, ['#%.6x' % rgb_value]])
self.mosi_bytes = []
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
+ self.ss_block = ss
elif self.state == 'GET SLAVE ADDR':
# Wait for an address write operation.
# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
# TODO: Handle read/write of only parts of these items.
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
+ self.put(self.ss_block, es, self.out_ann,
[9, ['Write date/time: %s' % d, 'Write: %s' % d,
'W: %s' % d]])
self.state = 'IDLE'
elif cmd == 'STOP':
d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
self.years, self.hours, self.minutes, self.seconds)
- self.put(self.block_start_sample, es, self.out_ann,
+ self.put(self.ss_block, es, self.out_ann,
[10, ['Read date/time: %s' % d, 'Read: %s' % d,
'R: %s' % d]])
self.state = 'IDLE'
def __init__(self, **kwargs):
self.state = 'IDLE'
self.ss, self.es = 0, 0
- self.bit_ss, self.bit_es = 0, 0
- self.cmd_ss, self.cmd_es = 0, 0
+ self.ss_bit, self.es_bit = 0, 0
+ self.ss_cmd, self.es_cmd = 0, 0
self.cmd_token = []
self.cmd_token_bits = []
self.is_acmd = False # Indicates CMD vs. ACMD
self.out_ann = self.register(srd.OUTPUT_ANN)
def putx(self, data):
- self.put(self.cmd_ss, self.cmd_es, self.out_ann, data)
+ self.put(self.ss_cmd, self.es_cmd, self.out_ann, data)
def putc(self, cmd, desc):
self.putx([cmd, ['%s: %s' % (self.cmd_str, desc)]])
def putb(self, data):
- self.put(self.bit_ss, self.bit_es, self.out_ann, data)
+ self.put(self.ss_bit, self.es_bit, self.out_ann, data)
def cmd_name(self, cmd):
c = acmd_names if self.is_acmd else cmd_names
# - CMD[00:00]: End bit (always 1)
if len(self.cmd_token) == 0:
- self.cmd_ss = self.ss
+ self.ss_cmd = self.ss
self.cmd_token.append(mosi)
self.cmd_token_bits.append(self.mosi_bits)
if len(self.cmd_token) < 6:
return
- self.cmd_es = self.es
+ self.es_cmd = self.es
t = self.cmd_token
return self.cmd_token_bits[5 - byte][bit]
# Bits[47:47]: Start bit (always 0)
- bit, self.bit_ss, self.bit_es = tb(5, 7)[0], tb(5, 7)[1], tb(5, 7)[2]
+ bit, self.ss_bit, self.es_bit = tb(5, 7)[0], tb(5, 7)[1], tb(5, 7)[2]
if bit == 0:
self.putb([134, ['Start bit: %d' % bit]])
else:
self.putb([135, ['Start bit: %s (Warning: Must be 0!)' % bit]])
# Bits[46:46]: Transmitter bit (1 == host)
- bit, self.bit_ss, self.bit_es = tb(5, 6)[0], tb(5, 6)[1], tb(5, 6)[2]
+ bit, self.ss_bit, self.es_bit = tb(5, 6)[0], tb(5, 6)[1], tb(5, 6)[2]
if bit == 1:
self.putb([134, ['Transmitter bit: %d' % bit]])
else:
# Bits[45:40]: Command index (BCD; valid: 0-63)
cmd = self.cmd_index = t[0] & 0x3f
- self.bit_ss, self.bit_es = tb(5, 5)[1], tb(5, 0)[2]
+ self.ss_bit, self.es_bit = tb(5, 5)[1], tb(5, 0)[2]
self.putb([134, ['Command: %s%d (%s)' % (s, cmd, self.cmd_name(cmd))]])
# Bits[39:8]: Argument
self.arg = (t[1] << 24) | (t[2] << 16) | (t[3] << 8) | t[4]
- self.bit_ss, self.bit_es = tb(4, 7)[1], tb(1, 0)[2]
+ self.ss_bit, self.es_bit = tb(4, 7)[1], tb(1, 0)[2]
self.putb([134, ['Argument: 0x%04x' % self.arg]])
# Bits[7:1]: CRC7
# TODO: Check CRC7.
crc = t[5] >> 1
- self.bit_ss, self.bit_es = tb(0, 7)[1], tb(0, 1)[2]
+ self.ss_bit, self.es_bit = tb(0, 7)[1], tb(0, 1)[2]
self.putb([134, ['CRC7: 0x%01x' % crc]])
# Bits[0:0]: End bit (always 1)
- bit, self.bit_ss, self.bit_es = tb(0, 0)[0], tb(0, 0)[1], tb(0, 0)[2]
+ bit, self.ss_bit, self.es_bit = tb(0, 0)[0], tb(0, 0)[1], tb(0, 0)[2]
self.putb([134, ['End bit: %d' % bit]])
if bit == 1:
self.putb([134, ['End bit: %d' % bit]])
# CMD1: SEND_OP_COND
self.putc(1, 'Send HCS info and activate the card init process')
hcs = (self.arg & (1 << 30)) >> 30
- self.bit_ss = self.cmd_token_bits[5 - 4][6][1]
- self.bit_es = self.cmd_token_bits[5 - 4][6][2]
+ self.ss_bit = self.cmd_token_bits[5 - 4][6][1]
+ self.es_bit = self.cmd_token_bits[5 - 4][6][2]
self.putb([134, ['HCS: %d' % hcs]])
self.state = 'GET RESPONSE R1'
# CMD9: SEND_CSD (128 bits / 16 bytes)
self.putc(9, 'Ask card to send its card specific data (CSD)')
if len(self.read_buf) == 0:
- self.cmd_ss = self.ss
+ self.ss_cmd = self.ss
self.read_buf.append(self.miso)
# FIXME
### if len(self.read_buf) < 16:
if len(self.read_buf) < 16 + 4:
return
- self.cmd_es = self.es
+ self.es_cmd = self.es
self.read_buf = self.read_buf[4:] # TODO: Document or redo.
self.putx([9, ['CSD: %s' % self.read_buf]])
# TODO: Decode all bits.
# CMD17: READ_SINGLE_BLOCK
self.putc(17, 'Read a block from address 0x%04x' % self.arg)
if len(self.read_buf) == 0:
- self.cmd_ss = self.ss
+ self.ss_cmd = self.ss
self.read_buf.append(self.miso)
if len(self.read_buf) < self.blocklen + 2: # FIXME
return
- self.cmd_es = self.es
+ self.es_cmd = self.es
self.read_buf = self.read_buf[2:] # FIXME
self.putx([17, ['Block data: %s' % self.read_buf]])
self.read_buf = []
# The R1 response token format (1 byte).
# Sent by the card after every command except for SEND_STATUS.
- self.cmd_ss, self.cmd_es = self.miso_bits[7][1], self.miso_bits[0][2]
+ self.ss_cmd, self.es_cmd = self.miso_bits[7][1], self.miso_bits[0][2]
self.putx([65, ['R1: 0x%02x' % res]])
def putbit(bit, data):
b = self.miso_bits[bit]
- self.bit_ss, self.bit_es = b[1], b[2]
+ self.ss_bit, self.es_bit = b[1], b[2]
self.putb([134, data])
# Bit 0: 'In idle state' bit
self.misodata = self.mosidata = 0
self.misobits = []
self.mosibits = []
- self.startsample = -1
+ self.ss_block = -1
self.samplenum = -1
self.cs_was_deasserted = False
self.oldcs = -1
meta=(int, 'Bitrate', 'Bitrate during transfers'))
def putw(self, data):
- self.put(self.startsample, self.samplenum, self.out_ann, data)
+ self.put(self.ss_block, self.samplenum, self.out_ann, data)
def putdata(self):
# Pass MISO and MOSI bits and then data to the next PD up the stack.
def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit of a dataword, save its sample number.
if self.bitcount == 0:
- self.startsample = self.samplenum
+ self.ss_block = self.samplenum
self.cs_was_deasserted = False
if self.have_cs:
active_low = (self.options['cs_polarity'] == 'active-low')
# Meta bitrate.
elapsed = 1 / float(self.samplerate)
- elapsed *= (self.samplenum - self.startsample + 1)
+ elapsed *= (self.samplenum - self.ss_block + 1)
bitrate = int(1 / elapsed * self.options['wordsize'])
- self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
+ self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
if cmd != 'START':
return
self.state = 'GET SLAVE ADDR'
- self.block_start_sample = ss
elif self.state == 'GET SLAVE ADDR':
self.chip = databyte
self.state = 'GET REG ADDR'
projects / libsigrokdecode.git / commitdiff