srd: fix probe mapping

diff --git a/type_logic.c b/type_logic.c
index 28c36707b9a789d9bf4dcf5191960661e9079163..7cea75bb4133c443274b133afed7c0eb25092144 100644 (file)
--- a/type_logic.c
+++ b/type_logic.c
@@ -48,10 +48,8 @@ PyObject *srd_logic_iternext(PyObject *self)
         */
        memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize,
                        logic->di->data_unitsize);
-       for (i = 0; i < logic->di->dec_num_probes; i++) {
-               probe_samples[logic->di->dec_probemap[i]] = sample & 0x01;
-               sample >>= 1;
-       }
+       for (i = 0; i < logic->di->dec_num_probes; i++)
+               probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
 
        /* Prepare the next samplenum/sample list in this iteration. */
        py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt);