};
static const uint32_t dslogic_devopts[] = {
- SR_CONF_CONTINUOUS | SR_CONF_SET,
+ SR_CONF_CONTINUOUS | SR_CONF_SET | SR_CONF_GET,
SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
SR_CONF_CONN | SR_CONF_GET,
case SR_CONF_EXTERNAL_CLOCK:
*data = g_variant_new_boolean(devc->dslogic_external_clock);
break;
+ case SR_CONF_CONTINUOUS:
+ *data = g_variant_new_boolean(devc->dslogic_continuous_mode);
+ break;
default:
return SR_ERR_NA;
}
case SR_CONF_EXTERNAL_CLOCK:
devc->dslogic_external_clock = g_variant_get_boolean(data);
break;
+ case SR_CONF_CONTINUOUS:
+ devc->dslogic_continuous_mode = g_variant_get_boolean(data);
+ break;
default:
ret = SR_ERR_NA;
}
* 13 1 = loopback test mode
* 12 1 = stream mode
* 11 1 = serial trigger
- * 8-12 unused
+ * 8-10 unused
* 7 1 = analog mode
* 6 1 = samplerate 400MHz
* 5 1 = samplerate 200MHz or analog mode
v16 = 1 << 14;
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
v16 = 1 << 13;
+ if (devc->dslogic_continuous_mode)
+ v16 |= 1 << 12;
if (devc->dslogic_external_clock)
v16 |= 1 << 1;