return std_dev_clear(di, clear_helper);
}
-static int set_cfg(const struct sr_dev_inst *sdi, const char *format, ...)
-{
- struct dev_context *devc = sdi->priv;
- va_list args;
- int ret;
-
- va_start(args, format);
- ret = sr_scpi_send_variadic(sdi->conn, format, args);
- va_end(args);
-
- if (ret != SR_OK)
- return SR_ERR;
-
- if (devc->model->series == RIGOL_DS1000) {
- /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
- sr_spew("delay %dms", 100);
- g_usleep(100000);
- return SR_OK;
- } else {
- return sr_scpi_get_opc(sdi->conn);
- }
-}
-
static int init(struct sr_context *sr_ctx)
{
return std_init(sr_ctx, di, LOG_PREFIX);
devc = sdi->priv;
if (devc->model->series != RIGOL_VS5000)
- set_cfg(sdi, ":KEY:LOCK DISABLE");
+ rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
if (scpi) {
if (sr_scpi_close(scpi) < 0)
return SR_ERR;
g_free(devc->trigger_slope);
devc->trigger_slope = g_strdup(tmp_u64 ? "POS" : "NEG");
- ret = set_cfg(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
break;
case SR_CONF_HORIZ_TRIGGERPOS:
t_dbl = g_variant_get_double(data);
* need to express this in seconds. */
t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
- ret = set_cfg(sdi, ":TIM:OFFS %s", buffer);
+ ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
break;
case SR_CONF_TIMEBASE:
g_variant_get(data, "(tt)", &p, &q);
devc->timebase = (float)p / q;
g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
devc->timebase);
- ret = set_cfg(sdi, ":TIM:SCAL %s", buffer);
+ ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
break;
}
}
tmp_str = "CHAN4";
else
tmp_str = (char *)devc->trigger_source;
- ret = set_cfg(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
break;
}
}
devc->vdiv[i] = (float)p / q;
g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
devc->vdiv[i]);
- return set_cfg(sdi, ":CHAN%d:SCAL %s", i + 1,
+ return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
buffer);
}
return SR_ERR_ARG;
if (!strcmp(tmp_str, coupling[j])) {
g_free(devc->coupling[i]);
devc->coupling[i] = g_strdup(coupling[j]);
- return set_cfg(sdi, ":CHAN%d:COUP %s", i + 1,
+ return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
devc->coupling[i]);
}
}
devc->enabled_analog_probes, probe);
if (probe->enabled != devc->analog_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1,
+ if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", probe->index + 1,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
devc->analog_channels[probe->index] = probe->enabled;
devc->enabled_digital_probes, probe);
/* Turn on LA module if currently off. */
if (!devc->la_enabled) {
- if (set_cfg(sdi, ":LA:DISP ON") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK)
return SR_ERR;
devc->la_enabled = TRUE;
}
}
if (probe->enabled != devc->digital_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index,
+ if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", probe->index,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
devc->digital_channels[probe->index] = probe->enabled;
/* Turn off LA module if on and no digital probes selected. */
if (devc->la_enabled && !devc->enabled_digital_probes)
- if (set_cfg(sdi, ":LA:DISP OFF") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK)
return SR_ERR;
if (devc->data_source == DATA_SOURCE_LIVE) {
- if (set_cfg(sdi, ":RUN") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
return SR_ERR;
} else if (devc->data_source == DATA_SOURCE_MEMORY) {
if (devc->model->series != RIGOL_DS2000) {
/* Apparently for the DS2000 the memory
* depth can only be set in Running state -
* this matches the behaviour of the UI. */
- if (set_cfg(sdi, ":RUN") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
return SR_ERR;
- if (set_cfg(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
+ if (rigol_ds_config_set(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
return SR_ERR;
- if (set_cfg(sdi, ":STOP") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
return SR_ERR;
}
if (rigol_ds_capture_start(sdi) != SR_OK)
probe = devc->channel_entry->data;
- if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d",
+ if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
probe->index + 1) != SR_OK)
return SR_ERR;
/* Check that the number of samples will be accepted */
- if (sr_scpi_send(sdi->conn, ":WAV:POIN %d;*OPC", devc->analog_frame_size) != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:POIN %d", devc->analog_frame_size) != SR_OK)
return SR_ERR;
if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
return SR_ERR;
sr_warn("Single shot acquisition failed, retrying...");
/* Sleep a bit, otherwise the single shot will often fail */
g_usleep(500000);
- sr_scpi_send(sdi->conn, ":SING");
+ rigol_ds_config_set(sdi, ":SING");
rigol_ds_set_wait_event(devc, WAIT_STOP);
return SR_ERR;
}
return SR_OK;
}
+/* Send a configuration setting. */
+SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
+{
+ struct dev_context *devc = sdi->priv;
+ va_list args;
+ int ret;
+
+ va_start(args, format);
+ ret = sr_scpi_send_variadic(sdi->conn, format, args);
+ va_end(args);
+
+ if (ret != SR_OK)
+ return SR_ERR;
+
+ if (devc->model->series == RIGOL_DS1000) {
+ /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
+ sr_spew("delay %dms", 100);
+ g_usleep(100000);
+ return SR_OK;
+ } else {
+ return sr_scpi_get_opc(sdi->conn);
+ }
+}
+
/* Start capturing a new frameset */
SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
{
sr_dbg("Starting data capture for frameset %lu of %lu",
devc->num_frames + 1, devc->limit_frames);
- if (sr_scpi_send(sdi->conn, ":WAV:FORM BYTE") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
return SR_ERR;
if (devc->data_source == DATA_SOURCE_LIVE) {
- if (sr_scpi_send(sdi->conn, ":WAV:MODE NORM") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
return SR_ERR;
rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
} else {
- if (sr_scpi_send(sdi->conn, ":WAV:MODE RAW") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
return SR_ERR;
- if (sr_scpi_send(sdi->conn, ":SING", devc->analog_frame_size) != SR_OK)
+ if (rigol_ds_config_set(sdi, ":SING", devc->analog_frame_size) != SR_OK)
return SR_ERR;
rigol_ds_set_wait_event(devc, WAIT_STOP);
}
return SR_ERR;
}
} else {
- if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d",
+ if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
probe->index + 1) != SR_OK)
return SR_ERR;
if (devc->data_source != DATA_SOURCE_LIVE) {
- if (sr_scpi_send(sdi->conn, ":WAV:RES") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
return SR_ERR;
- if (sr_scpi_send(sdi->conn, ":WAV:BEG") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
return SR_ERR;
rigol_ds_set_wait_event(devc, WAIT_BLOCK);
} else
* to the next channel causes an error. Fun with
* firmware...
*/
- sr_scpi_send(sdi->conn, ":WAV:END");
+ rigol_ds_config_set(sdi, ":WAV:END");
}
if (probe->type == SR_PROBE_ANALOG
if (devc->model->series >= RIGOL_DS1000Z) {
/* Vertical reference - not certain if this is the place to read it. */
for (i = 0; i < devc->model->analog_channels; i++) {
- if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d", i + 1) != SR_OK)
+ if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", i + 1) != SR_OK)
return SR_ERR;
if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", &devc->vert_reference[i]) != SR_OK)
return SR_ERR;