]> sigrok.org Git - libsigrok.git/commitdiff
dslogic: Refactored firmware selection into dslogic_fpga_firmware_upload
authorJoel Holdsworth <redacted>
Mon, 12 Jun 2017 19:19:44 +0000 (13:19 -0600)
committerUwe Hermann <redacted>
Mon, 19 Jun 2017 22:18:16 +0000 (00:18 +0200)
src/hardware/dslogic/api.c
src/hardware/dslogic/dslogic.c
src/hardware/dslogic/dslogic.h

index d5899d55d67b5a2573ac389b806124e23c540f48..75b24f90af86f478c07f51843e2996e40bb6db91 100644 (file)
@@ -332,7 +332,6 @@ static int dev_open(struct sr_dev_inst *sdi)
        struct sr_dev_driver *di = sdi->driver;
        struct sr_usb_dev_inst *usb;
        struct dev_context *devc;
-       const char *fpga_firmware = NULL;
        int ret;
        int64_t timediff_us, timediff_ms;
 
@@ -392,22 +391,8 @@ static int dev_open(struct sr_dev_inst *sdi)
                return SR_ERR;
        }
 
-       if (!strcmp(devc->profile->model, "DSLogic")) {
-               if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
-                       fpga_firmware = DSLOGIC_FPGA_FIRMWARE_3V3;
-               else
-                       fpga_firmware = DSLOGIC_FPGA_FIRMWARE_5V;
-       } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
-               fpga_firmware = DSLOGIC_PRO_FPGA_FIRMWARE;
-       } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
-               fpga_firmware = DSLOGIC_PLUS_FPGA_FIRMWARE;
-       } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
-               fpga_firmware = DSLOGIC_BASIC_FPGA_FIRMWARE;
-       } else if (!strcmp(devc->profile->model, "DSCope")) {
-               fpga_firmware = DSCOPE_FPGA_FIRMWARE;
-       }
 
-       if ((ret = dslogic_fpga_firmware_upload(sdi, fpga_firmware)) != SR_OK)
+       if ((ret = dslogic_fpga_firmware_upload(sdi)) != SR_OK)
                return ret;
 
        if (devc->cur_samplerate == 0) {
@@ -574,18 +559,7 @@ static int config_set(uint32_t key, GVariant *data,
                                break;
                        }
                }
-               if (!strcmp(devc->profile->model, "DSLogic")) {
-                       if (devc->voltage_threshold == DS_VOLTAGE_RANGE_5_V)
-                               ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
-                       else
-                               ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
-               } else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
-                       ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
-               } else if (!strcmp(devc->profile->model, "DSLogic Plus")) {
-                       ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PLUS_FPGA_FIRMWARE);
-               } else if (!strcmp(devc->profile->model, "DSLogic Basic")) {
-                       ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_BASIC_FPGA_FIRMWARE);
-               }
+               ret = dslogic_fpga_firmware_upload(sdi);
                break;
        case SR_CONF_EXTERNAL_CLOCK:
                devc->external_clock = g_variant_get_boolean(data);
index d0a98de279a6a54f1f1305a5005b4d25c48d5c67..4d466143f822495adf8d934473f16e81416b8f0a 100644 (file)
@@ -59,12 +59,13 @@ SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
        return SR_OK;
 }
 
-SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
-               const char *name)
+SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
 {
+       const char *name = NULL;
        uint64_t sum;
        struct sr_resource bitstream;
        struct drv_context *drvc;
+       struct dev_context *devc;
        struct sr_usb_dev_inst *usb;
        unsigned char *buf;
        ssize_t chunksize;
@@ -73,8 +74,27 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
        const uint8_t cmd[3] = {0, 0, 0};
 
        drvc = sdi->driver->context;
+       devc = sdi->priv;
        usb = sdi->conn;
 
+       if (!strcmp(devc->profile->model, "DSLogic")) {
+               if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
+                       name = DSLOGIC_FPGA_FIRMWARE_3V3;
+               else
+                       name = DSLOGIC_FPGA_FIRMWARE_5V;
+       } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
+               name = DSLOGIC_PRO_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
+               name = DSLOGIC_PLUS_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
+               name = DSLOGIC_BASIC_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSCope")) {
+               name = DSCOPE_FPGA_FIRMWARE;
+       } else {
+               sr_err("Failed to select FPGA firmware.");
+               return SR_ERR;
+       }
+
        sr_dbg("Uploading FPGA firmware '%s'.", name);
 
        result = sr_resource_open(drvc->sr_ctx, &bitstream,
index 93850107af28661bffb969331e4dca3baaf3c023..aac64aa05086d2e7c82c689073f648c6db6537fb 100644 (file)
@@ -148,8 +148,7 @@ struct dslogic_fpga_config {
 
 #pragma pack(pop)
 
-SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
-               const char *name);
+SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);